Datasheet

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DS32EL0124, DS32ELX0124

www.ti.com

SNLS284K –MAY 2008–REVISED APRIL 2013

DS32EL0124 , DS32ELX0124 125 MHz - 312.5 MHz FPGA-Link Deserializer with DDR LVDS

Parallel Interface

Check for Samples: DS32EL0124, DS32ELX0124

FEATURES

KEY SPECIFICATIONS

• 5-bit DDR LVDS Parallel Data Interface

• 1.25 to 3.125 Gbps Serial Data Rate

• Programmable Receive Equalization • 125 to 312.5 MHz DDR Parallel Clock

• Selectable DC-Balance Decoder • -40° to +85°C Temperature Range

• Selectable De-Scrambler • > 8 kV ESD (HBM) Protection

• Remote Sense for Automatic Detection and • 0.5 UI Minimum Input Jitter Tolerance (1.25

Negotiation of Link Status Gbps)

• No External Receiver Reference Clock

DESCRIPTION

Required

The DS32EL0124/DS32ELX0124 integrates clock

• LVDS Parallel Interface

and data recovery modules for high-speed serial

• Programmable LVDS Output Clock Delay

communication over FR-4 printed circuit board

• Supports Output Data-Valid Signaling

backplanes, balanced cables, and optical fiber. This

easy-to-use chipset integrates advanced signal and

• Supports Keep-Alive Clock Output

clock conditioning functions, with an FPGA friendly

• On Chip LC VCOs

interface.

• Redundant Serial Input (ELX device only)

The DS32EL0124/DS32ELX0124 deserializes up to

• Retimed Serial Output (ELX device only)

3.125 Gbps of high speed serial data to 5 LVDS

• Configurable PLL Loop Bandwidth

outputs without the need for an external reference

clock. With DC-balance decoding enabled, the

• Configurable via SMBus

application payload of 2.5 Gbps is deserialized to 4

• Loss of Lock and Error Reporting

LVDS outputs.

• 48-pin WQFN Package with Exposed DAP

The DS32EL0124/DS32ELX01214 deserializers

feature a remote sense capability to automatically

APPLICATIONS

signal link status conditions to its companion

• Imaging: Industrial, Medical Security, Printers

DS32EL0421/ELX0421 serializers without requiring

an additional feedback path.

• Displays: LED Walls, Commercial

The parallel LVDS interface of these devices reduce

• Video Transport

FPGA I/O pins, board trace count and alleviates EMI

• Communication Systems

issues, when compared to traditional single-ended

• Test and Measurement

wide bus interfaces.

• Industrial Bus

The DS32EL0124/ELX0124 is programmable through

a SMBus interface as well as through control pins.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (34 pages)

PAGE 1
DS32EL0124, DS32ELX0124 www.ti.com SNLS284K – MAY 2008 – REVISED APRIL 2013 DS32EL0124 , DS32ELX0124 125 MHz - 312.
PAGE 2
DS32EL0124, DS32ELX0124 SNLS284K – MAY 2008 – REVISED APRIL 2013 www.ti.com Typical Application DS32ELX0421 D1 R1 Redundant Driver Redundant Link Retimed Output LVDS Interface R0 Serial to Parallel Parallel to Serial Encoder D0 RT0 LVDS System Logic 5 LVDS 3.
PAGE 3
DS32EL0124, DS32ELX0124 VDD33 1 LT_EN 2 RXOUT4- RXOUT4+ RXOUT3- RXOUT3+ RXOUT2- RXOUT2+ RXOUT1- RXOUT1+ RXOUT0- RXOUT0+ RXCLKOUT- RXCLKOUT+ 47 46 45 44 43 42 41 40 39 38 37 SNLS284K – MAY 2008 – REVISED APRIL 2013 48 www.ti.
PAGE 4
DS32EL0124, DS32ELX0124 SNLS284K – MAY 2008 – REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS (continued) Pin Name Pin Number I/O, Type Description LT_EN 2 I, LVCMOS DS32ELX0124 only. When held high, retimed serialized high speed output is enabled. RX_MUX_SEL 12 I, LVCMOS DS32ELX0124 only. RX_MUX_SEL selects the input of the deserializer. 0 = RxIN0+/- selected 1 = RxIN1+/- selected VOD_CTRL 14 I, LVCMOS DS32ELX0124 only. VOD control.
PAGE 5
DS32EL0124, DS32ELX0124 www.ti.com SNLS284K – MAY 2008 – REVISED APRIL 2013 Absolute Maximum Ratings (1) (2) Supply Voltage (VDD33) −0.3V to +4V Supply Voltage (VDD25) -0.3V to +3.0V LVCMOS Input Voltage −0.3V to (VDD33 + 0.3V) LVCMOS Output Voltage -0.3V to (VDD33 + 0.3V) CML Input/Output Voltage -0.3V to 3.6V LVDS Output Voltage -0.3V to +3.6V Junction Temperature +125°C −65°C to +150°C Storage Temperature Range Lead Temperature Range Soldering (4 sec.
PAGE 6
DS32EL0124, DS32ELX0124 SNLS284K – MAY 2008 – REVISED APRIL 2013 www.ti.com LVCMOS Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Applies to LT_EN, GPIO0, GPIO1, GPIO2, RX_MUX_SEL, DC_B, RESET, RS, LOCK.
PAGE 7
DS32EL0124, DS32ELX0124 www.ti.com SNLS284K – MAY 2008 – REVISED APRIL 2013 SMBus Timing Specifications (continued) Over recommended operating supply and temperature ranges unless otherwise specified.
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DS32EL0124, DS32ELX0124 SNLS284K – MAY 2008 – REVISED APRIL 2013 www.ti.com LVDS Timing Specifications (continued) Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) Symbol tRLA Parameter Conditions Deserializer Lock Time tLVSK Min Typ Max Units (3) LVDS Output Skew 1.25 Gbps 22 2.5 Gbps 90 3.
PAGE 9
DS32EL0124, DS32ELX0124 www.ti.com SNLS284K – MAY 2008 – REVISED APRIL 2013 CML Retimed Loop Through Output Electrical Specifications, DS32ELX0124 Only Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter (1) (2) Conditions Min Typ Units 1.45 V VLTOD Output differential voltage VOD_CTRL resistor = 9.09 kΩ RLTOT Output termination 50Ω 40 50 60 75Ω 60 75 90 ΔRLTOT (1) (2) (3) 1.
PAGE 10
DS32EL0124, DS32ELX0124 SNLS284K – MAY 2008 – REVISED APRIL 2013 www.ti.com tROCP/2 +100 mV RXCLK -100 mV tROCH, tROCL tROHC tROSC Setup Hold RX[4:0] Figure 5. Deserializer (LVDS Interface) Setup/Hold and High/Low Times 3.0V RESET tRPLLS RxIN RxCLKOUT LOCK tRLAPL tRLA Figure 6. Reset to Lock Time Symbol N-1 Symbol N+1 Symbol N Symbol N+3 Symbol N+2 Symbol N+4 RXIN tRD RXCLK RX[0..4] Symbol N-4 Symbol N-3 Symbol N-2 Symbol N-1 Symbol N Figure 7.
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DS32EL0124, DS32ELX0124 www.ti.com SNLS284K – MAY 2008 – REVISED APRIL 2013 Last Bit In First Bit In E3 D3 C3 B3 A3 E2 D2 B2 C2 A2 E1 D1 B1 C1 A1 E0 D0 C0 B0 A0 High Speed Serial CML Input Previous Cycle Current Cycle Next Cycle Output Receive Clock LVDS Data-0 A0 A1 A2 A3 LVDS Data-1 B0 B1 B2 B3 LVDS Data-2 C0 C1 C2 C3 LVDS Data-3 D0 D1 D2 D3 LVDS Data-4 E0 E1 E2 E3 Figure 8.
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DS32EL0124, DS32ELX0124 SNLS284K – MAY 2008 – REVISED APRIL 2013 www.ti.com FUNCTIONAL DESCRIPTION POWER SUPPLIES The DS32EL0124 and DS32ELX0124 have several power supply pins, at 2.5V as well as 3.3V. It is important that these pins all be connected and properly bypassed. Bypassing should consist of parallel 4.7μF and 0.1μF capacitors as a minimum, with a 0.1μF capacitor on each power pin. A 22 μF capacitor is required on the VDDPLL pin which is connected to the 3.3V rail.
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DS32EL0124, DS32ELX0124 www.ti.com SNLS284K – MAY 2008 – REVISED APRIL 2013 REMOTE SENSE The remote sense feature can be used when a DS32EL0421 or DS32ELX0421 serializer is directly connected to a DS32EL0124 or DS32ELX0124 deserializer. Active components in the signal path between the serializer and the deserializer may interfere with the back channel signaling of the devices. When remote sense is enabled, the deserializer will cycle through five states to successfully establish a link and align the data.
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DS32EL0124, DS32ELX0124 SNLS284K – MAY 2008 – REVISED APRIL 2013 www.ti.com Power-On/Reset RxIN does not Exist or CDR Not Locked or Link Not Acquired Or Excessive Bit Errors IDLE RxIN detected RxIN detected and (RS:1, DC_B:0 or RS:1, DC_B:1) LINK DETECT CLOCK ACQUISITION Clock Recovered CDR Locked and (RS:1, DC_B:0 or RS:1, DC_B:1) LINK ACQUISITION Link Acquired NORMAL Figure 9.
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DS32EL0124, DS32ELX0124 www.ti.com SNLS284K – MAY 2008 – REVISED APRIL 2013 CML INPUT INTERFACING The DS32ELX0124 has two inputs to support redundancy and failover applications. Either input can be selected by using the RX_MUX_SEL pin or internal control registers. Whichever input is selected will be routed to the CDR of the deserializer. Only one input may be selected at a time. Within the CDR, the data is strobed at the center of the eye diagram(i.e. 0.5UI).
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DS32EL0124, DS32ELX0124 SNLS284K – MAY 2008 – REVISED APRIL 2013 www.ti.com When both Remote Sense and DC-Balance are disabled, RS and DC_B pins set to high, the LVDS lane alignment is not maintained. In this configuration, data formatting is handled by an FPGA or external source. In this mode the deserializer locks to incoming random data. To achieve lock during the clock acquisition phase, the incoming data should have a transition density of approximately 20% for a period of 200 µs.
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DS32EL0124, DS32ELX0124 www.ti.com 1. 2. 3. 4. 5. 6. 7. 8. 9. The The The The The The The The The SNLS284K – MAY 2008 – REVISED APRIL 2013 Host (Master) selects the device by driving its SMBus Chip Select (SMB_CS) signal HIGH. Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE. Device (Slave) drives the ACK bit (“0”). Host drives the 8-bit Register Address. Device drives an ACK bit (“0”). Host drive the 8-bit data byte. Device drives an ACK bit (“0”).
PAGE 18
DS32EL0124, DS32ELX0124 SNLS284K – MAY 2008 – REVISED APRIL 2013 www.ti.com SMBus Device FPGA Host 3V3 SMB_CS SDA LVCMOS GPIO SMBus Interface SCK 3V3 Figure 10. SMBus Configuration 1 SMBus Device FPGA Host SMBus Device SMBus Device SMB_CS SDA SCK SMB_CS SDA SCK SMB_CS SDA LVCMOS GPIO SMBus Interface SCK 3V3 Figure 11.
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DS32EL0124, DS32ELX0124 www.ti.com SNLS284K – MAY 2008 – REVISED APRIL 2013 PROPAGATION DELAY Once the deserializer is locked, the amount of time it takes for a signal to travel from the high speed CML serial input through the device and out via the DDR LVDS interface is defined to be the propagation delay. The propagation delay through the DS32EL0124/DS32ELX0124 due to the analog circuitry is considered negligible compared to the time delay caused by the digital components.
PAGE 20
DS32EL0124, DS32ELX0124 SNLS284K – MAY 2008 – REVISED APRIL 2013 www.ti.com HIGH SPEED COMMUNICATION MEDIA Using the deserializer’s integrated equalizer blocks in combination with the DS32EL0421 or DS32ELX0421’s integrated de-emphasis block allows data to be transmitted across a variety of media at high speeds. Factors that can limit device performance include excessive input clock jitter, noisy power rails, EMI from nearby noisy components and poor layout techniques.
PAGE 21
DS32EL0124, DS32ELX0124 www.ti.com SNLS284K – MAY 2008 – REVISED APRIL 2013 2.5V 3.3V 0.1 PF 0.1 PF RXOUT4 - 19 RXOUT3 + RXIN1 20 - RXOUT2 RXOUT1 RXOUT0 + - VOD_CTRL RXCLKOUT 27 + - DS32ELX0124 14 + - VDDPLL 22 PF 9.1 k: + - 3.3V 28 + + - LF_CP 30 nF 26 RESET LF_REF LOCK 6 21 TXOUT- DC_B 5 3.
PAGE 22
DS32EL0124, DS32ELX0124 SNLS284K – MAY 2008 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics The eye diagrams shown below illustrate the typical performance of the DS32ELX0124/DS32EL0124 configured with RS = 0, DC_B = 0, for the conditions listed below each figure. The PRBS-15 data was generated by a low cost FPGA, which used an LMK03000C to generate the various clock frequencies.
PAGE 23
DS32EL0124, DS32ELX0124 www.ti.com SNLS284K – MAY 2008 – REVISED APRIL 2013 Typical Performance Characteristics (continued) The eye diagrams shown below illustrate the typical performance of the DS32ELX0124/DS32EL0124 configured with RS = 0, DC_B = 0, for the conditions listed below each figure. The PRBS-15 data was generated by a low cost FPGA, which used an LMK03000C to generate the various clock frequencies.
PAGE 24
DS32EL0124, DS32ELX0124 SNLS284K – MAY 2008 – REVISED APRIL 2013 www.ti.com Register Map The register information for the deserializer is shown in the table below. Some registers have been omitted or marked as reserved; these are for internal testing and should not be written to. Some register bits require an override bit to be set before they can be written to.
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DS32EL0124, DS32ELX0124 www.ti.
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DS32EL0124, DS32ELX0124 SNLS284K – MAY 2008 – REVISED APRIL 2013 Addr (Hex) 2B Name Event Config 2C Reserved 2D Error Monitor www.ti.com Bits Field R/W Default Description 7:4 Reserved 0 3 Event Count Select R/W 0 0: Select CDR Event Counter for reading. Events include loss of signal detect or loss of CDR lock.
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DS32EL0124, DS32ELX0124 www.ti.
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DS32EL0124, DS32ELX0124 SNLS284K – MAY 2008 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision J (April 2013) to Revision K • 28 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 15-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing DS32EL0124SQ/NOPB WQFN RHS 48 DS32EL0124SQE/NOPB WQFN RHS DS32EL0124SQX/NOPB WQFN RHS DS32ELX0124SQ/NOPB WQFN SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 48 2500 330.0 16.4 7.3 7.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS32EL0124SQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 DS32EL0124SQE/NOPB WQFN RHS 48 250 213.0 191.0 55.0 DS32EL0124SQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 DS32ELX0124SQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 DS32ELX0124SQE/NOPB WQFN RHS 48 250 213.0 191.0 55.
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MECHANICAL DATA RHS0048A SQA48A (Rev B) www.ti.
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