Datasheet

DS34LV86T
www.ti.com
SNLS115D JUNE 2000REVISED APRIL 2013
DS34LV86T 3V Enhanced CMOS Quad Differential Line Receiver
Check for Samples: DS34LV86T
1
FEATURES
DESCRIPTION
The DS34LV86T is a high speed quad differential
Low Power CMOS Design (30 mW Typical)
CMOS receiver that meets the requirements of both
Interoperable With Existing 5V RS-422
TIA/EIA-422-B and ITU-T V.11. The CMOS
Networks
DS34LV86T features typical low static I
CC
of 9 mA
Industrial Temperature Range
which makes it ideal for battery powered and power
conscious applications. The Tri-State enables, EN,
Meets TIA/EIA-422-B (RS-422) and ITU-T V.11
allow the device to be disabled when not in use to
Recommendation
minimize power consumption. The dual enable
3.3V Operation
scheme allows for flexibility in turning receivers on
±7V Common Mode Range @ V
ID
= 3V
and off.
±10V Common Mode Range @ V
ID
= 0.2V
The receiver output (RO) is ensured to be High when
the inputs are left open. The receiver can detect
Receiver OPEN Input Failsafe Feature
signals as low as ±200 mV over the common mode
Ensured AC Parameter:
range of ±10V. The receiver outputs (RO) are
Maximum Receiver Skew: 4 ns
compatible with TTL and LVCMOS levels.
Transition Time: 10 ns
Pin Compatible With DS34C86T
32 MHz Toggle Frequency
>6.5k ESD Tolerance (HBM)
Available in SOIC Packaging
Connection Diagram
Figure 1. SOIC (Top View)
See Package Number D
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2000–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

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