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DS36954

www.ti.com

SNLS077C –JULY 1998–REVISED APRIL 2013

DS36954 Quad Differential Bus Transceiver

Check for Samples: DS36954

FEATURES

DESCRIPTION

The DS36954 is a low power, quad EIA-485

• Pinout for SCSI Interface

differential bus transceiver especially suited for high

• Compact 20-Pin PLCC or SOIC Package

speed, parallel, multipoint, I/O bus applications. A

• Meets EIA-485 Standard for Multipoint Bus

compact 20-pin surface mount PLCC or SOIC

Transmission

package provides high transceiver integration and a

very small PC board footprint.

• Greater than 60 mA Source/Sink Currents

Propagation delay skew between devices is specified

• Thermal Shutdown Protection

to aid in parallel interface designs—limits on

• Glitch-Free Driver Outputs on Power Up and

maximum and minimum delay times are verified.

Down

Five devices can implement a complete SCSI initiator

or target interface. Three transceivers in a package

are pinned out for data bus connections. The fourth

transceiver, with the flexibility provided by its

individual enables, can serve as a control bus

transceiver.

Connection Diagram

Logic Diagram

See Package Number FN (S-PQCC-J20)

See Package Number DW (R-PDSO-G20)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (17 pages)

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DS36954 www.ti.com SNLS077C – JULY 1998 – REVISED APRIL 2013 DS36954 Quad Differential Bus Transceiver Check for Samples: DS36954 FEATURES DESCRIPTION • • • The DS36954 is a low power, quad EIA-485 differential bus transceiver especially suited for high speed, parallel, multipoint, I/O bus applications. A compact 20-pin surface mount PLCC or SOIC package provides high transceiver integration and a very small PC board footprint.
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DS36954 SNLS077C – JULY 1998 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) Supply Voltage 7V Control Input Voltage VCC + 0.5V Driver Input Voltage VCC + 0.5V −10V to +15V Driver Output Voltage/Receiver Input Voltage Receiver Output Voltage 5.
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DS36954 www.ti.com SNLS077C – JULY 1998 – REVISED APRIL 2013 Electrical Characteristics (1)(2) (continued) Over Supply Voltage and Operating Temperature ranges, unless otherwise specified Symbol Parameter Conditions IIH Input High Current VIN = 2.4V (5) IIL Input Low Current VIN = 0.
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DS36954 SNLS077C – JULY 1998 – REVISED APRIL 2013 www.ti.com Switching Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.
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DS36954 www.ti.com SNLS077C – JULY 1998 – REVISED APRIL 2013 PARAMETER MEASUREMENT INFORMATION Figure 1. Driver VOD and VOC (3) Figure 2. Receiver VOH and VOL (2) (1) (1) The input pulse is supplied by a generator having the following characteristics: f = 1.0 MHz, 50% duty cycle, trand tf < 6.0 ns, ZO = 50Ω (2) CL includes probe and stray capacitance. Figure 3.
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DS36954 SNLS077C – JULY 1998 – REVISED APRIL 2013 www.ti.com (2) (1) S1 to OA for DI = 3V S1 to OB for DI = 0V (1) The input pulse is supplied by a generator having the following characteristics: f = 1.0 MHz, 50% duty cycle, trand tf < 6.0 ns, ZO = 50Ω. (2) CL includes probe and stray capacitance. Figure 5. Figure 6.
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DS36954 www.ti.com SNLS077C – JULY 1998 – REVISED APRIL 2013 Figure 8. Driver Enable and Disable Timing (tPZL, t PLZ) (1) (2) (1) The input pulse is supplied by a generator having the following characteristics: f = 1.0 MHz, 50% duty cycle, trand tf < 6.0 ns, ZO = 50Ω. (2) CL includes probe and stray capacitance. Figure 9. Figure 10. Receiver Differential Propagation Delay Timing (1) (4) (3) (2) (1) The input pulse is supplied by a generator having the following characteristics: f = 1.
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DS36954 SNLS077C – JULY 1998 – REVISED APRIL 2013 www.ti.com S1 1.5V S2 Open S3 Closed Figure 12. S1 −1.5V S2 Closed C3 Open Figure 13. S1 1.5V S2 Closed C3 Closed Figure 14. S1 −1.5V S2 Closed C3 Closed Figure 15.
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DS36954 www.ti.com SNLS077C – JULY 1998 – REVISED APRIL 2013 Tra, Trb, Tfa and Tfb are propagation delay measurements to the 20% and 80% levels. TCP = Crossing Point Figure 16.
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DS36954 SNLS077C – JULY 1998 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision B (April 2013) to Revision C • 10 Page Changed layout of National Data Sheet to TI format ............................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device DS36954MX/NOPB Package Package Pins Type Drawing SOIC DW 20 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 24.4 Pack Materials-Page 1 10.9 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 13.3 3.25 12.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS36954MX/NOPB SOIC DW 20 1000 367.0 367.0 45.
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MECHANICAL DATA MPLC004A – OCTOBER 1994 FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 20 PIN SHOWN Seating Plane 0.004 (0,10) 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D D1 0.020 (0,51) MIN 3 1 19 0.032 (0,81) 0.026 (0,66) 4 E 18 D2 / E2 E1 D2 / E2 8 14 0.021 (0,53) 0.013 (0,33) 0.007 (0,18) M 0.050 (1,27) 9 13 0.008 (0,20) NOM D/E D2 / E2 D1 / E1 NO. OF PINS ** MIN MAX MIN MAX MIN MAX 20 0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29) 28 0.
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