Datasheet

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DS64BR401

www.ti.com

SNLS304G –JUNE 2009–REVISED APRIL 2013

DS64BR401 Quad Bi-Directional Repeater with Equalization and

De-Emphasis

Check for Samples: DS64BR401

FEATURES

DESCRIPTION

The DS64BR401 is a quad lane bi-directional signal

• Quad lane bi-directional repeater up to 6.4

conditioning repeater for 6.0/3.0/1.5 Gbps SATA/SAS

Gbps rate

and other high-speed bus applications with data rates

• Signal conditioning on input and output for

up to 6.4 Gbps. The device performs both receive

extended reach

equalization and transmit de-emphasis on each of its

8 channels to compensate for channel loss, allowing

• Adjustable receive equalization up to +33 dB

maximum flexibility of physical placement within a

gain

system. The receiver's continuous time linear

• Adjustable transmit de-emphasis up to −12 dB

equalizer (CTLE) provides a boost of up to +33 dB at

• Adjustable transmit VOD (600 mVp-p to 1200

3 GHz and is capable of opening an input eye that is

mVp-p)

completely closed due to inter-symbol interference

(ISI) induced by the interconnect medium. The

• <0.25 UI of residual DJ at 6.4 Gbps with 40”

transmitter features a programmable output de-

FR4 trace

emphasis driver and allows amplitude voltage levels

• Automatic de-emphasis scaling based on rate

to be selected from 600 mVp-p to 1200 mVp-p to suit

detect

multiple application scenarios. This Low Power

• SATA/SAS: OOB signal pass-through,

Differential Signaling (LPDS) output driver is a power

efficient implementation that maintains compatibility

– <3 ns (typ) envelope distortion

with AC coupled CML receiver. The programmable

• Adjustable electrical IDLE detect threshold

settings can be applied via pin settings or SMBus

• Low power (100 mW/channel), per-channel

interface.

power down

To enable seamless upgrade from SAS/SATA 3.0

• Programmable via pin selection or SMBus

Gbps to 6.0 Gbps data rates without compromising

interface

physical reach, DS64BR401 automatically detects the

incoming data rate and selects the optimal de-

• Single supply operation at 2.5V ±5%

emphasis pulse width. The device detects the out-of-

• >6 kV HBM ESD Rating

band (OOB) idle and active signals of the SAS/SATA

• 3.3V LVCMOS input tolerant for SMBus

specification and passes through with minimum signal

interface

distortion.

• High speed signal flow–thru pinout package:

With a typical power consumption of 200 mW/lane

54-pin WQFN (10 mm x 5.5 mm)

(100 mW/channel) at 6.4 Gbps, and control to turn-off

unused channels, the DS64BR401 is part of Texas

APPLICATIONS

Instruments' PowerWise family of energy efficient

devices.

• SATA (1.5, 3.0 and 6 Gbps)

• SAS (1.5, 3.0 and 6 Gbps)

• XAUI (3.125 Gbps), RXAUI (6.25 Gbps)

• sRIO – Serial Rapid I/O

• Fibre Channel (4.25 Gbps)

• 10GBase-CX4, InfiniBand 4x (SDR & DDR)

• QSFP active copper cable modules

• High-speed active cable and FR-4 backplane

traces

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (36 pages)

PAGE 1
DS64BR401 www.ti.com SNLS304G – JUNE 2009 – REVISED APRIL 2013 DS64BR401 Quad Bi-Directional Repeater with Equalization and De-Emphasis Check for Samples: DS64BR401 FEATURES DESCRIPTION • The DS64BR401 is a quad lane bi-directional signal conditioning repeater for 6.0/3.0/1.5 Gbps SATA/SAS and other high-speed bus applications with data rates up to 6.4 Gbps.
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DS64BR401 SNLS304G – JUNE 2009 – REVISED APRIL 2013 www.ti.
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DS64BR401 www.ti.
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DS64BR401 SNLS304G – JUNE 2009 – REVISED APRIL 2013 www.ti.com Table 1. PIN DESCRIPTIONS Pin Name Pin Number I/O, Type Pin Descriptions Differential High Speed I/O's IA_0+, IA_0- , IA_1+, IA_1-, IA_2+, IA_2-, IA_3+, IA_3- 10, 12, 15, 17, 11 13 16 18 I, CML Inverting and non-inverting CML differential inputs to the equalizer. A gated on-chip 50Ω termination resistor connects INA_n+ to VDD and INA_n- to VDD when enabled.
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DS64BR401 www.ti.com SNLS304G – JUNE 2009 – REVISED APRIL 2013 Table 1. PIN DESCRIPTIONS (continued) Pin Name Pin Number I/O, Type Pin Descriptions TXIDLEA,TXIDLEB 24, 25 I, Float, LVCMOS TXIDLEA/B, 3–level controls the driver output. TXIDLEA/B = 0 disables the signal detect/squelch function for all A/B outputs. TXIDLEA/B = 1 forces the outputs to be muted (electrical idle).
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DS64BR401 SNLS304G – JUNE 2009 – REVISED APRIL 2013 ABSOLUTE MAXIMUM RATINGS www.ti.com (1) (2) Supply Voltage (VDD) -0.5V to +3.0V LVCMOS Input/Output Voltage -0.5V to +4.0V CML Input Voltage -0.5V to (VDD+0.5V) LPDS Output Voltage -0.5V to (VDD+0.5V) Analog (SD_TH) -0.5V to (VDD+0.5V) Junction Temperature +125°C Storage Temperature -40°C to +125°C Maximum Package Power Dissipation at 25°C NJY Package 4.21 W Derate NJY Package 52.
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DS64BR401 www.ti.com SNLS304G – JUNE 2009 – REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS Over recommended operating supply and temperature ranges with default register settings unless other specified. Symbol Parameter Conditions Min (1) Typ Max Units PWDN = 0, EQx = 0, DEMx = 0 dB, K28.5 pattern VOD = 1.0 Vp-p 758 950 mW PWDN = 1, ENSMB = 0 0.92 1.125 mW 2.0 3.
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DS64BR401 SNLS304G – JUNE 2009 – REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Over recommended operating supply and temperature ranges with default register settings unless other specified. (1) Symbol VOCM TTX-RF Parameter Conditions Min Output Common-Mode Voltage Single-ended measurement DC-Coupled with 50Ω termination, Transmitter Rise/ Fall Time 20% to 80% of differential output voltage, measured within 1” from output pins, (2) (4) , Figure 2 Typ VDD – 1.
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DS64BR401 www.ti.com SNLS304G – JUNE 2009 – REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS (continued) Over recommended operating supply and temperature ranges with default register settings unless other specified. (1) Symbol DJ2 Parameter Typ Max Units Tx Launch Amplitude = 0.8 to 1.2 Vp–p, 12 meters (30 AWG), EQx[1:0] = 1F, DEMx[1:0] = 0 dB, VOD = 1.0 Vp-p, K28.5, SD_TH = float, (5) 0.05 0.15 UIP-P Tx Launch Amplitude = 0.8 to 1.
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DS64BR401 SNLS304G – JUNE 2009 – REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS — SERIAL MANAGEMENT BUS INTERFACE (continued) Over recommended operating supply and temperature ranges unless other specified. Symbol Parameter TBUF Bus Free Time Between Stop and Start Condition THD:STA Hold time after (Repeated) Start Condition. After this period, the first clock is generated. Conditions Min Typ Max Units 4.7 µs 4.0 µs At IPULLUP, Max TSU:STA Repeated Start Condition Setup Time 4.
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DS64BR401 www.ti.com SNLS304G – JUNE 2009 – REVISED APRIL 2013 TIMING DIAGRAMS Figure 2. LPDS Output Transition Times Figure 3. Propagation Delay Timing Diagram Figure 4. Idle Timing Diagram tLOW tR tHIGH SCL tHD:STA tBUF tHD:DAT tF tSU:STA tSU:DAT tSU:STO SDA SP ST ST SP Figure 5.
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DS64BR401 SNLS304G – JUNE 2009 – REVISED APRIL 2013 www.ti.com FUNCTIONAL DESCRIPTION The DS64BR401 is a quad repeater optimized for backplane trace or cable interconnect up to 6.4 Gbps. The DS64BR401 operates in two modes: Pin Control Mode (ENSMB = 0) and SMBus Mode (ENSMB = 1). Pin Control Mode: When in pin mode (ENSMB = 0) , the repeater is configurable with external pins. Equalization and de-emphasis can be selected via pin for each side independently.
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DS64BR401 www.ti.com SNLS304G – JUNE 2009 – REVISED APRIL 2013 Table 3. Equalization Settings with GST=2 for Pins or SMBus Registers (continued) EQ1 ( EQ0 ( 1) 1) EQ Setting EQ Gain (dB) GST[4 :3] BST[2: 0] 1.5 GHz 3.0 GHz 10 111 14.5 22.0 Suggested Use Table 4. Equalization Settings with GST=3 for Pins or SMBus Registers EQ1 ( EQ0 ( EQ Gain (dB) 1.5 GHz 3.0 GHz Suggested Use 000 7.7 14.6 25” FR4 (4-mil trace) or 6m (30 AWG) 001 10.1 18.4 11 010 12.2 21.2 11 011 14.4 24.
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DS64BR401 SNLS304G – JUNE 2009 – REVISED APRIL 2013 www.ti.com Table 5. De-Emphasis Input Select Pins for A and B ports (3–Level Input) (continued) RATE DEM1 DEM0 (1) (1) 1/F 0 1 1/F 1 0 1/F 1/F 1/F 1/F 1 0 1 F 1 F F 0 1/F F 1 1/F F F DeEmphasis Level (typ) DE Pulse Width (typ) -3.
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DS64BR401 www.ti.com SNLS304G – JUNE 2009 – REVISED APRIL 2013 250 825 VDD = 2.5V TA = 25°C 200 PD - POWER DISSIPATION (mW) ELECTRICAL IDLE DETECT THRESHOLD (DIFF mVp-p) TYPICAL PERFORMANCE CURVES 150 100 50 0 0 10k 20k 30k 40k 50k 60k 70k 80k SD_TH RESISTOR VALUE (:) VDD = 2.5 V, TA = 25°C 800 775 750 725 600 800 1000 1200 VOD - DIFFERENTIAL OUTPUT VOLTAGE (mVp-p) Figure 6. Typical Idle Threshold vs. SD_TH resistor value Figure 7. Typical Power Dissipation (PD) vs.
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DS64BR401 SNLS304G – JUNE 2009 – REVISED APRIL 2013 www.ti.com When SMBus is enabled, the DS64BR401 must use one of the following De-emphasis settings (Table 8). The driver de-emphasis value is set on a per channel basis using 8 different registers. Each register (0x11, 0x18, 0x1F, 0x26, 0x2E, 0x35, 0x3C, 0x43) requires one of the following De-emphasis settings when in SMBus mode. Table 8.
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DS64BR401 www.ti.com SNLS304G – JUNE 2009 – REVISED APRIL 2013 – Write 30'h to address 0x0F, 0x16, 0x1D, 0x24, 0x2C, 0x33, 0x3A, 0x41. 4. Set VOD = 1.0V for all channels (CH0–CH7): – Write 0F'h to address 0x10, 0x17, 0x1E, 0x25, 0x2D, 0x34, 0x3B, 0x42. IDLE AND RATE DETECTION TO EXTERNAL PINS The functions of IDLE and RATE detection to external pins for monitoring can be supported in SMBus mode.
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DS64BR401 SNLS304G – JUNE 2009 – REVISED APRIL 2013 www.ti.com Table 9. SMBus Register Map Address Register Name Bit (s) Field Type Default Description 0x00 Reset 7:1 Reserved R/W 0x00 Set bits to 0.
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DS64BR401 www.ti.com SNLS304G – JUNE 2009 – REVISED APRIL 2013 Table 9. SMBus Register Map (continued) Address Register Name Bit (s) Field Type Default Description 0x11 CH0 - CHB0 DE Control 7:0 CH0 OB0 DEM R/W 0x03 OB0 DEM Control [7]: DEM TYPE (Compatibility = 0 / Enhanced = 1) [6:0]: DEM Level Control Pin [DEM1 DEM0] = Register [TYPE] [Level Control] = Hex Value 00 = 00000001 = 01'h = 0.0 dB 01 = 00111000 = 38'h = −3.5 dB 0F = 10001000 = 88'h = −6.0 dB 01 = 10010000 = 90'h = −9.
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DS64BR401 SNLS304G – JUNE 2009 – REVISED APRIL 2013 www.ti.com Table 9. SMBus Register Map (continued) Address Register Name Bit (s) Field Type Default Description 0x18 CH1 - CHB1 DE Control 7:0 CH1 OB1 DEM R/W 0x03 OB1 DEM Control [7]: DEM TYPE (Compatibility = 0 / Enhanced = 1) [6:0]: DEM Level Control Pin [DEM1 DEM0] = Register [TYPE] [Level Control] = Hex Value 00 = 00000001 = 01'h = 0.0 dB 01 = 00111000 = 38'h = −3.5 dB 0F = 10001000 = 88'h = −6.0 dB 01 = 10010000 = 90'h = −9.
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DS64BR401 www.ti.com SNLS304G – JUNE 2009 – REVISED APRIL 2013 Table 9. SMBus Register Map (continued) Address Register Name Bit (s) Field Type Default Description 0x1F CH2 - CHB2 DE Control 7:0 CH2 OB2 DEM R/W 0x03 OB2 DEM Control [7]: DEM TYPE (Compatibility = 0 / Enhanced = 1) [6:0]: DEM Level Control Pin [DEM1 DEM0] = Register [TYPE] [Level Control] = Hex Value 00 = 00000001 = 01'h = 0.0 dB 01 = 00111000 = 38'h = −3.5 dB 0F = 10001000 = 88'h = −6.0 dB 01 = 10010000 = 90'h = −9.
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DS64BR401 SNLS304G – JUNE 2009 – REVISED APRIL 2013 www.ti.com Table 9. SMBus Register Map (continued) Address Register Name Bit (s) Field Type Default Description 0x26 CH3 - CHB3 DE Control 7:0 CH3 OB3 DEM R/W 0x03 OB3 DEM Control [7]: DEM TYPE (Compatibility = 0 / Enhanced = 1) [6:0]: DEM Level Control Pin [DEM1 DEM0] = Register [TYPE] [Level Control] = Hex Value 00 = 00000001 = 01'h = 0.0 dB 01 = 00111000 = 38'h = −3.5 dB 0F = 10001000 = 88'h = −6.0 dB 01 = 10010000 = 90'h = −9.
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DS64BR401 www.ti.com SNLS304G – JUNE 2009 – REVISED APRIL 2013 Table 9. SMBus Register Map (continued) Address Register Name Bit (s) Field Type Default Description 0x2E CH4 - CHA0 DE Control 7:0 CH4 OA0 DEM R/W 0x03 OA0 DEM Control [7]: DEM TYPE (Compatibility = 0 / Enhanced = 1) [6:0]: DEM Level Control Pin [DEM1 DEM0] = Register [TYPE] [Level Control] = Hex Value 00 = 00000001 = 01'h = 0.0 dB 01 = 00111000 = 38'h = −3.5 dB 0F = 10001000 = 88'h = −6.0 dB 01 = 10010000 = 90'h = −9.
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DS64BR401 SNLS304G – JUNE 2009 – REVISED APRIL 2013 www.ti.com Table 9. SMBus Register Map (continued) Address Register Name Bit (s) Field Type Default Description 0x35 CH5 - CHA1 DE Control 7:0 CH5 OA1 DEM R/W 0x03 OA1 DEM Control [7]: DEM TYPE (Compatibility = 0 / Enhanced = 1) [6:0]: DEM Level Control Pin [DEM1 DEM0] = Register [TYPE] [Level Control] = Hex Value 00 = 00000001 = 01'h = 0.0 dB 01 = 00111000 = 38'h = −3.5 dB 0F = 10001000 = 88'h = −6.0 dB 01 = 10010000 = 90'h = −9.
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DS64BR401 www.ti.com SNLS304G – JUNE 2009 – REVISED APRIL 2013 Table 9. SMBus Register Map (continued) Address Register Name Bit (s) Field Type Default Description 0x3C CH6 - CHA2 DE Control 7:0 CH6 OA2 DEM R/W 0x03 OA2 DEM Control [7]: DEM TYPE (Compatibility = 0 / Enhanced = 1) [6:0]: DEM Level Control Pin [DEM1 DEM0] = Register [TYPE] [Level Control] = Hex Value 00 = 00000001 = 01'h = 0.0 dB 01 = 00111000 = 38'h = −3.5 dB 0F = 10001000 = 88'h = −6.0 dB 01 = 10010000 = 90'h = −9.
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DS64BR401 SNLS304G – JUNE 2009 – REVISED APRIL 2013 www.ti.com Table 9. SMBus Register Map (continued) Address Register Name Bit (s) Field Type Default Description 0x43 CH7 - CHA3 DE Control 7:0 CH7 OA3 DEM R/W 0x03 OA3 DEM Control [7]: DEM TYPE (Compatibility = 0 / Enhanced = 1) [6:0]: DEM Level Control Pin [DEM1 DEM0] = Register [TYPE] [Level Control] = Hex Value 00 = 00000001 = 01'h = 0.0 dB 01 = 00111000 = 38'h = −3.5 dB 0F = 10001000 = 88'h = −6.0 dB 01 = 10010000 = 90'h = −9.
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DS64BR401 www.ti.com SNLS304G – JUNE 2009 – REVISED APRIL 2013 APPLICATION INFORMATION GENERAL RECOMMENDATIONS The DS64BR401 is a high performance circuit capable of delivering excellent performance. Careful attention must be paid to the details associated with high-speed design as well as providing a clean power supply. Refer to the LVDS Owner's Manual for more detailed information on high speed design tips to address signal integrity design issues.
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DS64BR401 SNLS304G – JUNE 2009 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE EYE-DIAGRAM CHARACTERISTIC Pattern Generator VTX = 1.0Vp-p, PRBS7 Coax SMA adaptor DS64BR401EVK miniSAS4x Cable miniSAS4x Cable SMA adaptor Coax Scope Instrument TP1 TP0 Figure 9. Test Setup Connection Diagram 28 Figure 10. TP0: Input — After 5m 26–AWG Cable at 6 Gbps Figure 11. TP1: Output — After 1m 28–AWG Cable at 6 Gbps (EQ[1:0] = F0, DEM[1:0] = 01) Figure 12.
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DS64BR401 www.ti.com SNLS304G – JUNE 2009 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision F (April 2013) to Revision G • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DS64BR401SQ/NOPB WQFN NJY 54 2000 330.0 16.4 5.8 10.3 1.0 12.0 16.0 Q1 DS64BR401SQE/NOPB WQFN NJY 54 250 178.0 16.4 5.8 10.3 1.0 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS64BR401SQ/NOPB WQFN NJY 54 2000 367.0 367.0 38.0 DS64BR401SQE/NOPB WQFN NJY 54 250 213.0 191.0 55.
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PACKAGE OUTLINE NJY0054A WQFN SCALE 2.000 WQFN 5.6 5.4 B A PIN 1 INDEX AREA 0.5 0.3 0.3 0.2 10.1 9.9 DETAIL OPTIONAL TERMINAL TYPICAL 0.8 MAX C SEATING PLANE 2X 4 SEE TERMINAL DETAIL 3.51±0.1 19 (0.1) 27 28 18 50X 0.5 7.5±0.1 2X 8.5 1 45 54 PIN 1 ID (OPTIONAL) 46 54X 54X 0.5 0.3 0.3 0.2 0.1 0.05 C A C B 4214993/A 07/2013 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2.
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EXAMPLE BOARD LAYOUT NJY0054A WQFN WQFN (3.51) SYMM 54X (0.6) 54 54X (0.25) SEE DETAILS 46 1 45 50X (0.5) (7.5) SYMM (9.8) (1.17) TYP 2X (1.16) 28 18 ( 0.2) TYP VIA 19 27 (1) TYP (5.3) LAND PATTERN EXAMPLE SCALE:8X 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND METAL SOLDER MASK OPENING SOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) METAL SOLDER MASK DEFINED SOLDER MASK DETAILS 4214993/A 07/2013 NOTES: (continued) 4.
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EXAMPLE STENCIL DESIGN NJY0054A WQFN WQFN SYMM METAL TYP (0.855) TYP 46 54 54X (0.6) 54X (0.25) 1 45 50X (0.5) (1.17) TYP SYMM (9.8) 12X (0.97) 18 28 19 27 12X (1.51) (5.3) SOLDERPASTE EXAMPLE BASED ON 0.125mm THICK STENCIL EXPOSED PAD 67% PRINTED SOLDER COVERAGE BY AREA SCALE:10X 4214993/A 07/2013 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.
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