Datasheet

DS90C032
www.ti.com
SNLS094D JUNE 1998REVISED APRIL 2013
DS90C032 LVDS Quad CMOS Differential Line Receiver
Check for Samples: DS90C032
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FEATURES
DESCRIPTION
TheDS90C032 is a quad CMOS differential line
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>155.5 Mbps (77.7 MHz) switching rates
receiver designed for applications requiring ultra low
Accepts small swing (350 mV) differential
power dissipation and high data rates. The device
signal levels
supports data rates in excess of 155.5 Mbps (77.7
Ultra low power dissipation
MHz) and uses Low Voltage Differential Signaling
(LVDS) technology.
600 ps maximum differential skew (5V, 25°C)
TheDS90C032 accepts low voltage (350 mV)
6.0 ns maximum propagation delay
differential input signals and translates them to
Industrial operating temperature range
CMOS (TTL compatible) output levels. The receiver
Military operating temperature range option
supports a TRI-STATE function that may be used to
Available in surface mount packaging (SOIC)
multiplex outputs. The receiver also supports OPEN,
shorted, and terminated (100Ω) input Failsafe with
and (LCCC)
the addition of external failsafe biasing. Receiver
Pin compatible with DS26C32A, MB570
output will be HIGH for both Failsafe conditions.
(PECL), and 41LF (PECL)
TheDS90C032 and companion line driver
Supports OPEN input fail-safe
(DS90C031) provide a new alternative to high power
Supports short and terminated input fail-safe
pseudo-ECL devices for high speed point-to-point
with the addition of external failsafe biasing
interface applications.
Compatible with IEEE 1596.3 SCI LVDS
standard
Conforms to ANSI/TIA/EIA-644 LVDS standard
Available to Standard Microcircuit Drawing
(SMD) 5962-95834
Connection Diagram
Dual-In-Line
Figure 1. See Package Number D (R-PDSO-G16)
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PRODUCTION DATA information is current as of publication date.
Copyright © 1998–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

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