Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - serialisers FPD-Link, LVDS TQFP 48

DS90C124, DS90C241

www.ti.com

SNLS209L –NOVEMBER 2005–REVISED APRIL 2013

DS90C241 and DS90C124 5-MHz to 35-MHz DC-Balanced 24-Bit FPD-Link II Serializer and

Deserializer

Check for Samples: DS90C124, DS90C241

FEATURES

DESCRIPTION

The DS90C241 and DS90C124 chipset translates a

• 5-MHz to 35-MHz clock embedded and DC-

24-bit parallel bus into a fully transparent data and

Balancing 24:1 and 1:24 data transmissions

control LVDS serial stream with embedded clock

• User defined pre-emphasis driving ability

information. This single serial stream simplifies

through external resistor on LVDS outputs and

transferring a 24-bit bus over PCB traces or over

capable to drive up to 10-meter shielded

cable by eliminating the skew problems between

twisted-pair cable

parallel data and clock paths. It saves system cost by

narrowing data paths, which in turn reduces PCB

• User-selectable clock edge for parallel data on

layers, cable width, and connector size and pins.

both transmitter and receiver

The DS90C241 and DS90C124 incorporate LVDS

• Internal DC balancing encode and decode –

signaling on the high-speed I/O. LVDS provides a

Supports AC-coupling interface with no

low-power and low-noise environment for reliably

external coding required

transferring data over a serial transmission path. By

• Individual power-down controls for both

optimizing the serializer output edge rate for the

transmitter and receiver

operating frequency range, EMI is further reduced.

• Embedded clock CDR (clock and data

In addition, the device features pre-emphasis to boost

recovery) on receiver and no external source

signals over longer distances using lossy cables.

of reference clock needed

Internal DC balanced encoding and decoding

• All codes RDL (random data lock) to support

supports AC-coupled interconnects.

live-pluggable applications

• LOCK output flag to ensure data integrity at

receiver side

• Balanced T

SETUP

and T

HOLD

between RCLK and

RDATA on receiver side

• PTO (progressive turn-on) LVCMOS outputs to

reduce EMI and minimize SSO effects

• All LVCMOS inputs and control pins have

internal pulldown

• On-chip filters for PLLs on transmitter and

receiver

• Temperature range –40°C to +105°C

• Greater than 8-kV HBM ESD tolerant

• Meets AEC-Q100 compliance

• Power supply range 3.3V ± 10%

• 48-pin TQFP package

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (31 pages)

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DS90C124, DS90C241 www.ti.com SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 DS90C241 and DS90C124 5-MHz to 35-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Check for Samples: DS90C124, DS90C241 FEATURES DESCRIPTION • The DS90C241 and DS90C124 chipset translates a 24-bit parallel bus into a fully transparent data and control LVDS serial stream with embedded clock information.
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DS90C124, DS90C241 SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 www.ti.
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DS90C124, DS90C241 www.ti.com SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 Recommended Operating Conditions Min Nom Max Supply Voltage (VCC) 3.0 3.3 3.
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DS90C124, DS90C241 SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 www.ti.com Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Pin/Freq. Min Typ Max Units 2.0 VCC V GND 0.8 V −0.8 −1.5 V LVCMOS/LVTTL DC SPECIFICATIONS VIH High Level Voltage VIL Low Level Input Voltage VCL Input Clamp Voltage IIN Input Current ICL = −18 mA (1) VIN = 0V or 3.
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DS90C124, DS90C241 www.ti.com SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 Electrical Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Pin/Freq.
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DS90C124, DS90C241 SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 www.ti.com Serializer Timing Requirements for TCLK Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Max Units tTCP Transmit Clock Period 28.6 T 200 ns tTCIH Transmit Clock High Time 0.4T 0.5T 0.6T ns tTCIL Transmit Clock Low Time 0.4T 0.5T 0.6T ns tCLKT TCLK Input Transition Time 3 6 ns 33 ps (RMS) Max Units 0.6 ns 0.
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DS90C124, DS90C241 www.ti.com SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 Deserializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions tRCP Receiver out Clock Period tRDC RCLK Duty Cycle tCLH LVCMOS Low-to-High Transition Time tCHL LVCMOS High-to-Low Transition Time tROS ROUT (7:0) Setup Data to RCLK (Group 1) tROH CL = 8 pF (lumped load) (Figure 11) (1) Pin/Freq.
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DS90C124, DS90C241 SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 www.ti.com Device Pin Name Signal Pattern RCLK ODD ROUT EVEN ROUT Figure 2. Deserializer Output Checkerboard Pattern DOUT+ 10 pF Differential Signal 100: 80% 80% 20% Vdiff = 0V 20% DOUT10 pF tLLHT tLHLT Vdiff = (DOUT+) - (DOUT-) Figure 3. Serializer LVDS Output Load and Transition Times 80% VDD 80% TCLK 20% 20% tCLKT 0V tCLKT Figure 4.
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DS90C124, DS90C241 www.ti.com SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 Parasitic package and Trace capcitance DOUT+ 5 pF 100: DOUTDEN tLZD DEN VCC/2 (single-ended) 0V VCC/2 0V CLK1 CLK1 tTCP tTCP DOUT± (differential) 200 mV DCA tZLD 200 mV DCA DCA DCA $OO GDWD ³0´V DCA DCA DCA DCA tHZD DEN VCC/2 (single-ended) 0V VCC/2 0V $OO GDWD ³1´V tZHD DCA 200 mV DCA DCA DCA DCA DCA DCA DCA 200 mV DOUT± (differential) tTCP tTCP CLK0 CLK0 Figure 6.
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DS90C124, DS90C241 DIN SYMBOL N www.ti.com SYMBOL N+1 SYMBOL N+2 | | SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 SYMBOL N+3 | tSD TCLK 23 0 1 2 23 0 1 2 23 0 1 2 STOP START BIT BIT 23 0 STOP BIT SYMBOL N 1 2 | | 2 STOP START BIT BIT SYMBOL N-1 | | 1 | | 0 | | DOUT0-23 DCA, DCB STOP START BIT BIT SYMBOL N-2 | | STOP START BIT BIT SYMBOL N-3 SYMBOL N-4 23 Figure 8.
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DS90C124, DS90C241 www.ti.com SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 23 0 1 2 23 0 1 2 23 0 1 2 STOP BIT | | 2 STOP START BIT BIT SYMBOL N+3 | | 1 STOP START BIT BIT SYMBOL N+2 | | 0 STOP START BIT BIT SYMBOL N+1 SYMBOL N | | START BIT RIN0-23 DCA, DCB 23 tDD RCLK SYMBOL N-3 ROUT0-23 SYMBOL N-2 SYMBOL N-1 SYMBOL N Figure 12.
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DS90C124, DS90C241 SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 www.ti.com tLOW RCLK tHIGH VDD/2 ROUT [7:0] VDD/2 VDD/2 tROS tROH (group 1) (group 1) Data Valid Before RCLK Data Valid After RCLK VDD/2 1/2 UI ROUT [15:8], LOCK 1/2 UI VDD/2 tROS tROH (group 2) (group 2) Data Valid Before RCLK Data Valid After RCLK VDD/2 1/2 UI ROUT [23:16] 1/2 UI VDD/2 tROS tROH (group 3) (group 3) Data Valid Before RCLK Data Valid After RCLK VDD/2 Figure 15.
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DS90C124, DS90C241 www.ti.com SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 PIN ASSIGNMENTS DS90C241 Serializer Pin Descriptions Pin # Pin Name I/O Description LVCMOS PARALLEL INTERFACE PINS 4-1, DIN[23:0] 48-44, 41-32, 29-25 LVCMOS_I Transmitter Parallel Interface Data Input Pins. Tie LOW if unused, do not float. 10 LVCMOS_I Transmitter Parallel Interface Clock Input Pin. Strobe edge set by TRFB configuration pin.
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DS90C124, DS90C241 SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 www.ti.
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DS90C124, DS90C241 www.ti.com Pin # 2 SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 Pin Name RESRVD I/O LVCMOS_I Description Reserved. This pin MUST be tied LOW. LVDS SERIAL INTERFACE PINS 41 RIN+ LVDS_I Receiver LVDS True (+) Input This input is intended to be terminated with a 100Ω load to the RIN+ pin. The interconnect should be AC Coupled to this pin with a 100 nF capacitor.
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DS90C124, DS90C241 SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 www.ti.
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DS90C124, DS90C241 www.ti.com SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 Step 1: When VCC is applied to both Serializer and/or Deserializer, the respective outputs are held in TRI-STATE and internal circuitry is disabled by on-chip power-on circuitry. When VCC reaches VCC OK (2.2V) the PLL in Serializer begins locking to a clock input. For the Serializer, the local clock is the transmit clock, TCLK. The Serializer outputs are held in TRI-STATE while the PLL locks to the TCLK.
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DS90C124, DS90C241 SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 www.ti.com POWERDOWN The Powerdown state is a low power sleep mode that the Serializer and Deserializer may use to reduce power when no data is being transferred. The TPWDNB and RPWDNB are used to set each device into power down mode, which reduces supply current to the µA range. The Serializer enters powerdown when the TPWDNB pin is driven low.
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DS90C124, DS90C241 www.ti.com SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 Receiver Termination Option 1 A single 100 Ohm termination resistor is placed across the RIN± pins (see Figure 20). This provides the signal termination at the Receiver inputs. Other options may be used to increase noise tolerance. Receiver Termination Option 2 For additional EMI tolerance, two 50 Ohm resistors may be used in place of the single 100 Ohm resistor.
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DS90C124, DS90C241 SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 www.ti.com NOISE MARGIN The Deserializer noise margin is the amount of input jitter (phase noise) that the Deserializer can tolerate and still reliably recover data. Various environmental and systematic factors include: • Serializer: TCLK jitter, VCC noise (noise bandwidth and out-of-band noise) • Media: ISI, VCM noise • Deserializer: VCC noise For a graphical representation of noise margin, please see Figure 16.
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DS90C124, DS90C241 www.ti.com SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of these external bypass capacitors, usually in the range of 20-30 MHz range.
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DS90C124, DS90C241 SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 www.ti.com DS90C241 (SER) VDDDR DIN0 DIN1 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 C5 C3 C6 C7 Serial LVDS Interface R1 GPO DOUTTPWDNB DEN TRFB DCAOFF DCBOFF VODSEL PRE RESRVD R2 C2 DOUT+ TCLK TPWDNB = System GPO DEN = High (ON) TRFB = High (Rising edge) VODSEL = Low (400mV) PRE = Rpre RESRVD = Low DCAOFF = Low DCBOFF = Low C4 VDDIT VDDL VDDT DIN16 DIN17 DIN18 DIN19 DIN20 DIN21 DIN22 DIN23 3.
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DS90C124, DS90C241 www.ti.com SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 DS90C124 (DES) 3.3V VDDIR C5 VDDPR0 VDDPR1 C6 VDDOR1 VDDOR2 VDDOR3 C7 C9 RIN+ Serial LVDS Interface R1 RINC10 3.3V GPO RPWDNB REN RRFB RPWDNB = System GPO REN = High (ON) RRFB = High (Rising edge) RESRVD = Low RESRVD C1 C2 C3 C4 VDDR0 VDDR1 C8 C1 to C8 = 0.1 PF to 0.01 PF C9 = 100 nF; 50 WVDC, NPO or X7R C10 = 100 nF; 50 WVDC, NPO or X7R R1 = 100: 3.
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DS90C124, DS90C241 SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 www.ti.com VDD 0.1 PF 0.1 PF RIN+ RPU DS90C241 50: DS90C124 100: 4.7 nF RPD 50: RIN- 0.1 PF 0.1 PF Figure 24. Receiver Termination Option 3 Truth Tables Table 1. DS90C241 Serializer Truth Table TPWDNB (Pin 9) DEN (Pin 18) Tx PLL Status (Internal) LVDS Outputs (Pins 19 and 20) L X X Hi Z Hi Z H L X H H Not Locked Hi Z H H Locked Serialized Data with Embedded Clock Table 2.
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DS90C124, DS90C241 www.ti.com SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision K (April 2013) to Revision L • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 12-Apr-2013 (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DS90C124IVSX/NOPB TQFP PFB 48 1000 330.0 16.4 9.3 9.3 2.2 12.0 16.0 Q2 DS90C124QVSX/NOPB TQFP PFB 48 1000 330.0 16.4 9.3 9.3 2.2 12.0 16.0 Q2 DS90C241IVSX/NOPB TQFP PFB 48 1000 330.0 16.4 9.3 9.3 2.2 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS90C124IVSX/NOPB TQFP PFB 48 1000 367.0 367.0 38.0 DS90C124QVSX/NOPB TQFP PFB 48 1000 367.0 367.0 38.0 DS90C241IVSX/NOPB TQFP PFB 48 1000 367.0 367.0 38.0 DS90C241QVSX/NOPB TQFP PFB 48 1000 367.0 367.0 38.
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MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°– 7° 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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