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DS90C3201

www.ti.com

SNLS192D –APRIL 2005–REVISED APRIL 2013

DS90C3201 3.3V 8 MHz to 135 MHz Dual FPD-Link Transmitter

Check for Samples: DS90C3201

FEATURES

DESCRIPTION

The DS90C3201 is a 3.3V single/dual FPD-Link 10-

• Up to 9.45Gbit/s data throughput

bit color transmitter is designed to be used in Liquid

• 8 MHz to 135 MHz input clock support

Crystal Display TVs, LCD Monitors, Digital TVs, and

• Supports up to QXGA panel resolutions

Plasma Display Panel TVs. The DS90C3201 is

designed to interface between the digital video

• Supports HDTV resolutions and frame rates up

processor and the display device using the low-

to 1920 x 1080p

power, low-EMI LVDS (Low Voltage Differential

• LVDS 30-bit, 24-bit or 18-bit color data outputs

Signaling) interface. The DS90C3201 converts up to

• Supports single pixel and dual pixel interfaces

70 bits of LVCMOS/LVTTL data into ten LVDS data

streams. The transmitter can be programmed

• Supports spread spectrum clocking

clocking data with rising edge or falling edge clock.

• Two-wire serial communication interface

Optional two-wire serial programming allows fine

• Programmable clock edge and control strobe

tuning in development and production environments.

select

At a transmitted clock frequency of 135 MHz, 70 bits

of LVCMOS/LVTTL data are transmitted at an

• Power down mode

effective rate of 945 Mbps per LVDS channel. Using

• +3.3V supply voltage

a 135 MHz clock, the data throughput is 9.45Gbit/s

• 128-pin TQFP

(945Mbytes/s). This allows the dual 10-bit LVDS

Transmitter to support HDTV resolutions.

• Compliant to TIA/EIA-644-A-2001 LVDS

Standard

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (22 pages)

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DS90C3201 www.ti.com SNLS192D – APRIL 2005 – REVISED APRIL 2013 DS90C3201 3.3V 8 MHz to 135 MHz Dual FPD-Link Transmitter Check for Samples: DS90C3201 FEATURES DESCRIPTION • • • • The DS90C3201 is a 3.3V single/dual FPD-Link 10bit color transmitter is designed to be used in Liquid Crystal Display TVs, LCD Monitors, Digital TVs, and Plasma Display Panel TVs.
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DS90C3201 SNLS192D – APRIL 2005 – REVISED APRIL 2013 www.ti.com Block Diagram TXOA [6:0] 7 TXOA-/+ 7 TXOB-/+ TXOB[6:0] TXOE[6:0] TXEA[6:0] TXEB[6:0] TXEC[6:0] TXED[6:0] TXEE[6:0] TXOC-/+ 7 7 7 7 TXOE-/+ TXEA-/+ TXEB-/+ 7 TXEC-/+ 7 TXED-/+ 7 TCLKIN TXOD-/+ LVD S O UTPUT TXOD [6:0] 7 LVTTL PARALLEL-TO-LVDS LVCMOS / LVTTL INPUT <69:0> TXOC [6:0] TXEE-/+ PLL TCLKOUT -/+ RFB PWDNB MODE0 MODE1 S2CLK S2DAT Figure 1.
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DS90C3201 www.ti.com SNLS192D – APRIL 2005 – REVISED APRIL 2013 2 channels of video data (10-bit each for RGB for each channel, totaling 60 bits) and control signals (HSYNC, VSYNC, DE and two user-defined signals) along with clock signal. The dual high speed LVDS channels supports single pixel in-single pixel out and dual pixel in-dual pixel out transmission modes.
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DS90C3201 SNLS192D – APRIL 2005 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) −0.3V to +4V Supply Voltage (VDD) LVCMOS/LVTTL Input Voltage −0.3V to (VDD + 0.3V) LVCMOS/LVTTL Output Voltage −0.3V to (VDD + 0.3V) LVDS Output Voltage −0.3V to (VDD + 0.
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DS90C3201 www.ti.com SNLS192D – APRIL 2005 – REVISED APRIL 2013 Electrical Characteristics (1) (2) (3) (continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol VOS Parameter Conditions Offset Voltage (Programmable register) ΔVOS Change in VOS between complimentary output states IOS Output Short Circuit Current Min Typ Max Unit RL = 100Ω, Register addr 28d/1ch bit [3:2] (TXE) = 00b, bit [1:0] (TXO) = 00b, (Default) 1.0 1.2 1.
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DS90C3201 SNLS192D – APRIL 2005 – REVISED APRIL 2013 www.ti.com Transmitter Switching Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Min Typ Max Unit TPPos3 Transmitter Output Pulse Position for bit 3 (6th bit) (Figure 15) 5 UI − 0.2 5 5 UI + 0.2 UI (1) TPPos2 Transmitter Output Pulse Position for bit 2 (7th bit) (Figure 15) 6 UI − 0.2 6 6 UI + 0.
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DS90C3201 www.ti.com SNLS192D – APRIL 2005 – REVISED APRIL 2013 Two-Wire Serial Communication Interface (continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol BUF Parameter Bus Free Time Conditions Min RP = 4.7KΩ, CL = 50pF 13 Typ Max Unit us AC Timing Diagrams SCD:TF SCD:TR fSC SC:LOW SC:HIGH | S2CLK HD:STO HD:STA | S2DAT Data in | SU:STA SC:SD | SD:SC | S2DAT Data out SCL:SD Figure 3.
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DS90C3201 SNLS192D – APRIL 2005 – REVISED APRIL 2013 www.ti.com AC Timing Diagrams (continued) 250 Incr. Pattern (max) Worst Case (max) ICC (mA) 200 150 100 Worst Case (typ) 50 0 Incr. Pattern (typ) 0 20 40 60 80 100 120 140 160 FREQUENCY (MHz) Figure 6. Typical and Max ICC with Worst Case and Incremental Test Pattern Figure 7. LVDS Transition Times 80% 80% 20% 20% TCIT TCIT Figure 8.
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DS90C3201 www.ti.com SNLS192D – APRIL 2005 – REVISED APRIL 2013 AC Timing Diagrams (continued) 1.5V PWDNB 3.15V VDD | TPLLS TCLK IN VDIFF = 0V TCLK OUT Figure 10. Phase Lock Loop Set Time 1.5V | PWDNB TxCLK IN | TPDD VDIFF = 0V TCLK OUT 500 mV GND Figure 11. Transmitter Powerdown Delay TxCLK IN TxIN RFB = 0 RFB = 1 Figure 12. LVTLL Input Programmable Strobe Select Ideal Bit Start Ideal Bit Stop 1 UI = TCIP/7 Ideal Pulse Width Figure 13.
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DS90C3201 SNLS192D – APRIL 2005 – REVISED APRIL 2013 www.ti.
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DS90C3201 www.ti.
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DS90C3201 SNLS192D – APRIL 2005 – REVISED APRIL 2013 www.ti.
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DS90C3201 www.ti.com SNLS192D – APRIL 2005 – REVISED APRIL 2013 DS90C3201 PIN DESCRIPTIONS (continued) Pin No.
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DS90C3201 SNLS192D – APRIL 2005 – REVISED APRIL 2013 www.ti.com DS90C3201 PIN DESCRIPTIONS (continued) 14 Pin No.
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DS90C3201 www.ti.com SNLS192D – APRIL 2005 – REVISED APRIL 2013 DS90C3201 PIN DESCRIPTIONS (continued) Pin No.
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DS90C3201 SNLS192D – APRIL 2005 – REVISED APRIL 2013 www.ti.com APPLICATION INFORMATION Two-Wire Serial Communication Interface Description The DS90C3201 operates as a slave on the Serial Bus, so the S2CLK line is an input (no clock is generated by the DS90C3201) and the S2DAT line is bi-directional. DS90C3201 has a fixed 7bit slave address. The address is not user configurable in anyway. A zero in front of the register address is required.
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DS90C3201 www.ti.com SNLS192D – APRIL 2005 – REVISED APRIL 2013 The master must generate a “Start” by sending the 7-bit slave address plus a 0 and wait for acknowledge from DS90C3201. When DS90C3201 acknowledges (the 1st ACK) that the master is calling, the master then sends the data register address byte and waits for acknowledge from the slave. When the slave acknowledges (the 2nd ACK), the master sends the data byte and wait for acknowledge from the slave.
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DS90C3201 SNLS192D – APRIL 2005 – REVISED APRIL 2013 www.ti.com Table 1.
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DS90C3201 www.ti.com SNLS192D – APRIL 2005 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision C (April 2013) to Revision D • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.com 12-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) DS90C3201VS/NOPB ACTIVE Package Type Package Pins Package Drawing Qty TQFP PDT 128 90 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) CU SN Level-3-260C-168 HR (4) 0 to 70 DS90C3201VS (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
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MECHANICAL DATA MPQF013 – NOVEMBER 1995 PDT (S-PQFP-G128) PLASTIC QUAD FLATPACK 0,23 0,13 0,40 96 0,05 M 65 97 64 128 33 1 0,13 NOM 32 12,40 TYP Gage Plane 14,05 SQ 13,95 16,10 SQ 15,90 0,05 MIN 0,25 0°– 5° 0,75 0,45 1,05 0,95 Seating Plane 0,08 1,20 MAX 4087726/A 11/95 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice.
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