Datasheet

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DS90C3202

www.ti.com

SNLS191D –APRIL 2005–REVISED APRIL 2013

DS90C3202 3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver

Check for Samples: DS90C3202

FEATURES

DESCRIPTION

The DS90C3202 is a 3.3V single/dual FPD-Link 10-

• Up to 9.45 Gbit/s data throughput

bit color receiver is designed to be used in Liquid

• 8 MHz to 135 MHz input clock support

Crystal Display TVs, LCD Monitors, Digital TVs, and

• Supports up to QXGA panel resolutions

Plasma Display Panel TVs. The DS90C3202 is

designed to interface between the digital video

• Supports HDTV panel resolutions and frame

processor and the display device using the low-

rates up to 1920 x 1080p

power, low-EMI LVDS (Low Voltage Differential

• LVDS 30-bit, 24-bit or 18-bit color data inputs

Signaling) interface. The DS90C3202 converts up to

• Supports single pixel and dual pixel interfaces

ten LVDS data streams back into 70 bits of parallel

LVCMOS/LVTTL data. The receiver can be

• Supports spread spectrum clocking

programmed with rising edge or falling edge clock.

• Two-wire serial communication interface

Optional wo-wire serial programming allows fine

• Programmable clock edge and control strobe

tuning in development and production environments.

select

With an input clock at 135 MHz, the maximum

transmission rate of each LVDS line is 945 Mbps, for

• Power down mode

an aggregate throughput rate of 9.45 Gbps (945

• +3.3V supply voltage

Mbytes/s). This allows the dual 10-bit LVDS Receiver

• 128-pin TQFP Package

to support resolutions up to HDTV.

• Compliant to TIA/EIA-644-A-2001 LVDS

Standard

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (26 pages)

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DS90C3202 www.ti.com SNLS191D – APRIL 2005 – REVISED APRIL 2013 DS90C3202 3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver Check for Samples: DS90C3202 FEATURES DESCRIPTION • • • • The DS90C3202 is a 3.3V single/dual FPD-Link 10bit color receiver is designed to be used in Liquid Crystal Display TVs, LCD Monitors, Digital TVs, and Plasma Display Panel TVs.
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DS90C3202 SNLS191D – APRIL 2005 – REVISED APRIL 2013 www.ti.com Block Diagram 7 RXOA-/+ RXOA[6:0] 7 RXOB-/+ RXOB[6:0] 7 LVDS INPUT RXOD-/+ RXOE-/+ RXEA-/+ RXEB-/+ LVCMOS/LVTTL OUTPUT <69:0> RXOC[6:0] LVDS SERIAL-TO-LVTTL PARALLEL RXOC-/+ 7 RXOD[6:0] 7 RXOE[6:0] 7 RXEA[6:0] 7 RXEB[6:0] 7 RXEC-/+ RXEC[6:0] 7 RXED-/+ RXED[6:0] 7 RXEE-/+ RXEE[6:0] PLL RCLKIN-/+ RCLKOUT RFB PWDNB MODE0 MODE1 S2CLK S2DAT Figure 1.
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DS90C3202 www.ti.com SNLS191D – APRIL 2005 – REVISED APRIL 2013 2 channels of video data (10-bit each for RGB for each channel, totaling 60 bits) and control signals (HSYNC, VSYNC, DE and two user-defined signals) along with clock signal. The dual high speed LVDS channels supports single pixel in-single pixel out and dual pixel in-dual pixel out transmission modes.
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DS90C3202 SNLS191D – APRIL 2005 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) −0.3V to +4V Supply Voltage (VDD) LVCMOS/LVTTL Input Voltage −0.3V to (VDD + 0.3V) LVCMOS/LVTTL Output Voltage −0.3V to (VDD + 0.3V) LVDS Receiver Input Voltage −0.3V to (VDD + 0.
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DS90C3202 www.ti.com SNLS191D – APRIL 2005 – REVISED APRIL 2013 Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit CMOS/TTL DC SPECIFICATIONS (Rx outputs, control inputs and outputs) VIH High Level Input Voltage 2.0 VDD V VIL Low Level Input Voltage 0 0.
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DS90C3202 SNLS191D – APRIL 2005 – REVISED APRIL 2013 www.ti.com Receiver Switching Characteristics (1) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol CLHT Parameter Condition or Reference Min Typ Max Unit LVCMOS/LVTTL Low-to-High Transition Time, CL = 8pF, (Figure 7) (2) Register addr 28d/1ch, bit [2] (RCLK)=0b (Default), bit [1] (RXE) =0b (Default), bit [0] (RXO) =0b (Default) Rx clock out 1.45 2.10 ns Rx data out 2.40 3.
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DS90C3202 www.ti.com SNLS191D – APRIL 2005 – REVISED APRIL 2013 Two-Wire Serial Communication Interface Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 400 kHz fSC S2CLK Clock Frequency SC:LOW Clock Low Period RP = 4.7KΩ, CL = 50pF 1.5 SC:HIGH Clock High Period RP = 4.7KΩ, CL = 50pF 0.6 SCD:TR S2CLK and S2DAT Rise Time RP = 4.7KΩ, CL = 50pF SCD:TF S2CLK and S2DAT Fall Time RP = 4.
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DS90C3202 SNLS191D – APRIL 2005 – REVISED APRIL 2013 www.ti.com AC Timing Diagrams SCD:TF SCD:TR fSC SC:LOW SC:HIGH | S2CLK HD:STO HD:STA | S2DAT Data in | SU:STA SC:SD | SD:SC | S2DAT Data out SCL:SD Figure 3. Two-Wire Serial Communication Interface Timing Diagram Figure 4. “Worst Case” Test Pattern TCLKIN TXOA, TXEA TXOB, TXEB TXOC, TXEC TXOD, TXED TXOE, TXEE Figure 5. Incremental Test Pattern 600 Worst Case (max) 500 ICC (mA) 400 Worst Case (typ) 300 200 100 Incr.
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DS90C3202 www.ti.com SNLS191D – APRIL 2005 – REVISED APRIL 2013 AC Timing Diagrams (continued) Figure 7. LVCMOS/LVTTL Output Load and Transition Times 2V PWDNB 3.15V VDD | | RPLLS RCLK IN 2V RCLKOUT Figure 8. Receiver Phase Lock Loop Wake-up Time 1.5V PWDNB | | | Low RCLK IN RPDD RCLKOUT Low + RCLKIN + Rx IN - Rx OUT RPDL 1.5V | RCLKOUT (RFB=1) VDIFF = 0V | | | | | Figure 9. Powerdown Delay Figure 10.
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DS90C3202 SNLS191D – APRIL 2005 – REVISED APRIL 2013 www.ti.com AC Timing Diagrams (continued) RCLKOUT RxOUT RFB = 0 RFB = 1 Figure 11.
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DS90C3202 www.ti.com SNLS191D – APRIL 2005 – REVISED APRIL 2013 AC Timing Diagrams (continued) RCOP RCOL RCOH RFB=0 RCLK OUT VDD/2 VDD/2 RFB=1 RXEB,D[6:0] RXOA,C,E[6:0] VDD/2 RXEA,C,E[6:0] RXOB,D[6:0] VDD/2 VDD/2 1/2 UI 1/2 UI RegisterAddress 29d/1dh bit [2:1] = 00b Figure 14.
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DS90C3202 SNLS191D – APRIL 2005 – REVISED APRIL 2013 www.ti.com AC Timing Diagrams (continued) RCOP RFB=0 RCLK OUT Balanced RSRC / RHRC Register addr 29d/1dh bit[2:1]=00b (default) VDD/2 VDD/2 RFB=1 RCLK OUT RCLK OUT RCLK OUT VDD/2 VDD/2 VDD/2 RXEB,D[6:0] RXOA,C,E[6:0] VDD/2 RXEA,C,E[6:0] RXOB,D[6:0] VDD/2 Additional +0.
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DS90C3202 www.ti.
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DS90C3202 SNLS191D – APRIL 2005 – REVISED APRIL 2013 www.ti.
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DS90C3202 www.ti.
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DS90C3202 SNLS191D – APRIL 2005 – REVISED APRIL 2013 www.ti.com DS90C3202 PIN DESCRIPTIONS (continued) 16 Pin No.
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DS90C3202 www.ti.com SNLS191D – APRIL 2005 – REVISED APRIL 2013 DS90C3202 PIN DESCRIPTIONS (continued) Pin No.
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DS90C3202 SNLS191D – APRIL 2005 – REVISED APRIL 2013 www.ti.com DS90C3202 PIN DESCRIPTIONS (continued) 18 Pin No.
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DS90C3202 www.ti.com SNLS191D – APRIL 2005 – REVISED APRIL 2013 APPLICATION INFORMATION Two-Wire Serial Communication Interface Description The DS90C3202 operates as a slave on the Serial Bus, so the S2CLK line is an input (no clock is generated by the DS90C3202) and the S2DAT line is bi-directional. DS90C3202 has a fixed 7bit slave address. The address is not user configurable in anyway. A zero in front of the register address is required.
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DS90C3202 SNLS191D – APRIL 2005 – REVISED APRIL 2013 www.ti.com The master must generate a “Start” by sending the 7-bit slave address plus a 0 and wait for acknowledge from DS90C3202. When DS90C3202 acknowledges (the 1st ACK) that the master is calling, the master then sends the data register address byte and waits for acknowledge from the slave. When the slave acknowledges (the 2nd ACK), the master sends the data byte and wait for acknowledge from the slave.
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DS90C3202 www.ti.
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DS90C3202 SNLS191D – APRIL 2005 – REVISED APRIL 2013 22 www.ti.com Address R/W RESET Bit # Description Default Value 31d/1fh R/W None [7:6] 11; LVTTL Outputs available as long as "NO CLK" is at HIGH regardless PLL lock or not 10; LVTTL Outputs available after 1K of CLK cycles detected & PLL generated strobes are within 0.
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DS90C3202 www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 12-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) DS90C3202VS/NOPB ACTIVE Package Type Package Pins Package Drawing Qty TQFP PDT 128 90 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) CU SN Level-3-260C-168 HR (4) 0 to 70 DS90C3202VS (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
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MECHANICAL DATA MPQF013 – NOVEMBER 1995 PDT (S-PQFP-G128) PLASTIC QUAD FLATPACK 0,23 0,13 0,40 96 0,05 M 65 97 64 128 33 1 0,13 NOM 32 12,40 TYP Gage Plane 14,05 SQ 13,95 16,10 SQ 15,90 0,05 MIN 0,25 0°– 5° 0,75 0,45 1,05 0,95 Seating Plane 0,08 1,20 MAX 4087726/A 11/95 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice.
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