Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - customised TSSOP 48

DS90C363, DS90CF364

www.ti.com

SNLS123C –SEPTEMBER 1999–REVISED APRIL 2013

+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link–65 MHz,

+3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link–65 MHz

Check for Samples: DS90C363, DS90CF364

FEATURES

DESCRIPTION

The DS90C363 transmitter converts 21 bits of

• 20 to 65 MHz shift clock support

CMOS/TTL data into three LVDS (Low Voltage

• Programmable Transmitter (DS90C363) strobe

Differential Signaling) data streams. A phase-locked

select (Rising or Falling edge strobe)

transmit clock is transmitted in parallel with the data

• Single 3.3V supply

streams over a fourth LVDS link. Every cycle of the

transmit clock 21 bits of input data are sampled and

• Chipset (TX + RX) power consumption < 250

transmitted. The DS90CF364 receiver converts the

mW (typ)

LVDS data streams back into 21 bits of CMOS/TTL

• Power-down mode (< 0.5 mW total)

data. At a transmit clock frequency of 65 MHz, 18 bits

• Single pixel per clock XGA (1024×768) ready

of RGB data and 3 bits of LCD timing and control

data (FPLINE, FPFRAME, DRDY) are transmitted at

• Supports VGA, SVGA, XGA and higher

a rate of 455 Mbps per LVDS data channel. Using a

addressability

65 MHz clock, the data throughput is 170 Mbyte/sec.

• Up to 170 Megabyte/sec bandwidth

The Transmitter is offered with programmable edge

• Up to 1.3 Gbps throughput data strobes for convenient interface with a variety of

graphics controllers. The Transmitter can be

• Narrow bus reduces cable size and cost

programmed for Rising edge strobe or Falling edge

• 290 mV swing LVDS devices for low EMI

strobe through a dedicated pin. A Rising edge

• PLL requires no external components

Transmitter will inter-operate with a Falling edge

Receiver (DS90CF364) without any translation logic.

• Low profile 48-lead TSSOP package

• Falling edge data strobe Receiver This chipset is an ideal means to solve EMI and

cable size problems associated with wide, high speed

• Compatible with TIA/EIA-644 LVDS standard

TTL interfaces.

• ESD rating > 7 kV

• Operating Temperature: −40°C to +85°C

Block Diagrams

Figure 1. Application

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2TRI-STATE is a registered trademark of Texas Instruments.

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (19 pages)

PAGE 1
DS90C363, DS90CF364 www.ti.com SNLS123C – SEPTEMBER 1999 – REVISED APRIL 2013 +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link–65 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link–65 MHz Check for Samples: DS90C363, DS90CF364 FEATURES DESCRIPTION • • The DS90C363 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams.
PAGE 2
DS90C363, DS90CF364 SNLS123C – SEPTEMBER 1999 – REVISED APRIL 2013 www.ti.com Figure 2. DS90C363 Figure 3. DS90CF364 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) −0.3V to +4V Supply Voltage (VCC) CMOS/TTL Input Voltage −0.3V to (VCC + 0.3V) CMOS/TTL Output Voltage −0.3V to (VCC + 0.
PAGE 3
DS90C363, DS90CF364 www.ti.com SNLS123C – SEPTEMBER 1999 – REVISED APRIL 2013 Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit CMOS/TTL DC SPECIFICATIONS VIH High Level Input Voltage 2.0 VCC V VIL Low Level Input Voltage GND 0.8 V VOH High Level Output Voltage IOH = −0.4 mA VOL Low Level Output Voltage IOL = 2 mA 0.06 0.3 VCL Input Clamp Voltage ICL = −18 mA −0.79 −1.
PAGE 4
DS90C363, DS90CF364 SNLS123C – SEPTEMBER 1999 – REVISED APRIL 2013 www.ti.com Transmitter Switching Characteristics Over recommended operating supply and −40°C to +85°C ranges unless otherwise specified Symbol Parameter Min Typ Max Unit LLHT LVDS Low-to-High Transition Time (Figure 6 ) 0.75 1.5 ns LHLT LVDS High-to-Low Transition Time (Figure 6 ) 0.75 1.
PAGE 5
DS90C363, DS90CF364 www.ti.com SNLS123C – SEPTEMBER 1999 – REVISED APRIL 2013 AC Timing Diagrams A. The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O. B. Figure 4 and Figure 5 show a falling edge data strobe (TxCLK IN/RxCLK OUT). Figure 4.
PAGE 6
DS90C363, DS90CF364 SNLS123C – SEPTEMBER 1999 – REVISED APRIL 2013 www.ti.com AC Timing Diagrams (continued) Figure 6. DS90C363 (Transmitter) LVDS Output Load and Transition Times Figure 7. DS90CF364 (Receiver) CMOS/TTL Output Load and Transition Times Figure 8. DS90C363 (Transmitter) Input Clock Transition Time Measurements at Vdiff=0V TCCS measured between earliest and latest LVDS edges TxCLK Differential Low → High Edge Figure 9. DS90C363 (Transmitter) Channel-to-Channel Skew Figure 10.
PAGE 7
DS90C363, DS90CF364 www.ti.com SNLS123C – SEPTEMBER 1999 – REVISED APRIL 2013 AC Timing Diagrams (continued) Figure 11. DS90CF364 (Receiver) Setup/Hold and High/Low Times Figure 12. DS90C363 (Transmitter) Clock In to Clock Out Delay (Falling Edge Strobe) Figure 13. DS90CF364 (Receiver) Clock In to Clock Out Delay Figure 14.
PAGE 8
DS90C363, DS90CF364 SNLS123C – SEPTEMBER 1999 – REVISED APRIL 2013 www.ti.com AC Timing Diagrams (continued) Figure 15. DS90CF364 (Receiver) Phase Lock Loop Set Time Figure 16. Seven Bits of LVDS in One Clock Cycle Figure 17. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs Figure 18.
PAGE 9
DS90C363, DS90CF364 www.ti.com SNLS123C – SEPTEMBER 1999 – REVISED APRIL 2013 AC Timing Diagrams (continued) Figure 19. Receiver Power Down Delay Figure 20.
PAGE 10
DS90C363, DS90CF364 SNLS123C – SEPTEMBER 1999 – REVISED APRIL 2013 www.ti.com AC Timing Diagrams (continued) Figure 21.
PAGE 11
DS90C363, DS90CF364 www.ti.com SNLS123C – SEPTEMBER 1999 – REVISED APRIL 2013 PIN DESCRIPTIONS DS90C363 Pin Descriptions — FPD Link Transmitter Pin Name I/O No. Description TxIN I 21 TTL level input. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines—FPLINE, FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable). TxOUT+ O 3 Positive LVDS differentiaI data output. TxOUT− O 3 Negative LVDS differential data output. FPSHIFT IN I 1 TTL Ievel clock input.
PAGE 12
DS90C363, DS90CF364 SNLS123C – SEPTEMBER 1999 – REVISED APRIL 2013 www.ti.com Pin Diagrams Figure 23. DS90C363 See Package Number DGG (R-PDSO-G48) Figure 24. DS90CF364 See Package Number DGG (R-PDSO-G48) Truth Table Table 1.
PAGE 13
DS90C363, DS90CF364 www.ti.com SNLS123C – SEPTEMBER 1999 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision B (April 2013) to Revision C • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
PAGE 14
PACKAGE OPTION ADDENDUM www.ti.
PAGE 15
PACKAGE OPTION ADDENDUM www.ti.com 12-Apr-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PAGE 16
PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device DS90C363MTDX/NOPB Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TSSOP DGG 48 1000 330.0 24.4 8.6 13.2 1.6 12.0 24.0 Q1 DS90CF364MTDX/NOPB TSSOP DGG 48 1000 330.0 24.4 8.6 13.2 1.6 12.0 24.
PAGE 17
PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS90C363MTDX/NOPB TSSOP DGG 48 1000 367.0 367.0 45.0 DS90CF364MTDX/NOPB TSSOP DGG 48 1000 367.0 367.0 45.
PAGE 18
MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 19
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.