Datasheet

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DS90C365A

www.ti.com

SNLS181I –APRIL 2004–REVISED APRIL 2013

+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display Link-87.5 MHz

Check for Samples: DS90C365A

FEATURES

DESCRIPTION

The DS90C365A is a pin to pin compatible

• Pin-to-pin compatible to DS90C363,

replacement for DS90C363, DS90C363A and

DS90C363A and DS90C365

DS90C365. The DS90C365A has additional features

• No special start-up sequence required

and improvements making it an ideal replacement for

between clock/data and /PD pins. Input signals

DS90C363, DS90C363A and DS90C365. family of

(clock and data) can be applied either before

LVDS Transmitters.

or after the device is powered.

The DS90C365A transmitter converts 21 bits of

• Support Spread Spectrum Clocking up to

LVCMOS/LVTTL data into four LVDS (Low Voltage

100kHz frequency modulation & deviations of

Differential Signaling) data streams. A phase-locked

±2.5% center spread or -5% down spread.

transmit clock is transmitted in parallel with the data

streams over the fourth LVDS link. Every cycle of the

• “Input Clock Detection” feature will pull all

transmit clock 21 bits RGB of input data are sampled

LVDS pairs to logic low when input clock is

and transmitted. At a transmit clock frequency of 87.5

missing and when /PD pin is logic high.

MHz, 21 bits of RGB data and 3 bits of LCD timing

• 18 to 87.5 MHz shift clock support

and control data (FPLINE, FPFRAME, DRDY) are

• Tx power consumption < 146 mW (typ) at 87.5

transmitted at a rate of 612.5 Mbps per LVDS data

channel. Using a 87.5 MHz clock, the data throughput

MHz Grayscale

is 229.687 Mbytes/sec. This transmitter can be

• Tx Power-down mode < 37 uW (typ)

programmed for Rising edge strobe or Falling edge

• Supports VGA, SVGA, XGA, SXGA (dual pixel),

strobe through a dedicated pin. A Rising edge or

SXGA+ (dual pixel), UXGA (dual pixel).

Falling edge strobe transmitter will interoperate with a

Falling edge strobe FPDLink Receiver without any

• Narrow bus reduces cable size and cost

translation logic.

• Up to 1.785 Gbps throughput

This chipset is an ideal means to solve EMI and

• Up to 223.125 Megabytes/sec bandwidth

cable size problems associated with wide, high-speed

• 345 mV (typ) swing LVDS devices for low EMI

TTL interfaces with added Spead Spectrum Clocking

• PLL requires no external components

support..

• Compliant to TIA/EIA-644 LVDS standard

• Low profile 48-lead TSSOP package

Block Diagram

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2TRI-STATE is a registered trademark of Texas Instruments.

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (17 pages)

PAGE 1
DS90C365A www.ti.com SNLS181I – APRIL 2004 – REVISED APRIL 2013 +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display Link-87.5 MHz Check for Samples: DS90C365A FEATURES DESCRIPTION • The DS90C365A is a pin to pin compatible replacement for DS90C363, DS90C363A and DS90C365. The DS90C365A has additional features and improvements making it an ideal replacement for DS90C363, DS90C363A and DS90C365. family of LVDS Transmitters.
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DS90C365A SNLS181I – APRIL 2004 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) −0.3V to +4V Supply Voltage (VCC) CMOS/TTL Input Voltage −0.5V to (VCC + 0.3)V LVDS Driver Output Voltage −0.3V to (VCC + 0.
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DS90C365A www.ti.com SNLS181I – APRIL 2004 – REVISED APRIL 2013 Electrical Characteristics(1) (continued) Over recommended operating supply and temperature ranges unless otherwise specified.
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DS90C365A SNLS181I – APRIL 2004 – REVISED APRIL 2013 www.ti.com Transmitter Switching Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter Min (1) Typ Max Unit TPPos0 Transmitter Output Pulse Position (Figure 12) −0.25 0 +0.25 ns TPPos1 Transmitter Output Pulse Position 3.32 3.57 3.82 ns TPPos2 Transmitter Output Pulse Position 6.89 7.14 7.39 ns TPPos3 Transmitter Output Pulse Position 10.46 10.71 10.
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DS90C365A www.ti.com SNLS181I – APRIL 2004 – REVISED APRIL 2013 AC Timing Diagrams A. The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVCMOS/LVTTL I/O. B. Figure 1 and Figure 2 show a falling edge data strobe (TxCLK IN/RxCLK OUT). Figure 1. “Worst Case” Test Pattern A. The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern.
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DS90C365A SNLS181I – APRIL 2004 – REVISED APRIL 2013 www.ti.com AC Timing Diagrams (continued) Figure 5. DS90C365A (Transmitter) Input Clock Transition Time Figure 6. DS90C365A (Transmitter) Setup/Hold and High/Low Times with R_FB pin = GND (Falling Edge Strobe) Figure 7. DS90C365A (Transmitter) Clock In to Clock Out Delay with R_FB pin = VCC Figure 8. DS90C365A (Transmitter) Clock In to Clock Out Delay with R_FB pin = GND Figure 9.
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DS90C365A www.ti.com SNLS181I – APRIL 2004 – REVISED APRIL 2013 AC Timing Diagrams (continued) Figure 10. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90C365A Figure 11. Transmitter Power Down Delay Figure 12.
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DS90C365A SNLS181I – APRIL 2004 – REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS DS90C365A DGG0048A (TSSOP) Package Pin Descriptions — FPD Link Transmitter Pin Name I/O No. TxIN I 21 LVTTL level input. This includes: 6 Red, 6 Green, 6 Blue, and 3control lines—FPLINE, FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable). TxOUT+ O 3 Positive LVDS differentiaI data output. TxOUT− O 3 Negative LVDS differential data output. TxCLKIN I 1 LVTTL Ievel clock input. Pin name TxCLK IN.
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DS90C365A www.ti.com SNLS181I – APRIL 2004 – REVISED APRIL 2013 these cases should then be asserted once a stable clock is applied to the LVDS transmitter. Asserting the PWR DOWN pin will effectively place the device in reset and disable the PLL, enabling the LVDS Transmitter into a power saving standby mode. However, it is still generally a good practice to assert the PWR DOWN pin or reset the LVDS transmitter whenever the clock/data is stopped and reapplied but it is not mandatory for the DS90C365A.
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DS90C365A SNLS181I – APRIL 2004 – REVISED APRIL 2013 www.ti.com Typical Application Table 1.
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DS90C365A www.ti.com SNLS181I – APRIL 2004 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision H (April 2013) to Revision I • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device DS90C365AMTX/NOPB Package Package Pins Type Drawing TSSOP DGG 48 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 24.4 Pack Materials-Page 1 8.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 13.2 1.6 12.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS90C365AMTX/NOPB TSSOP DGG 48 1000 367.0 367.0 45.
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MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
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