DS90C383 DS90C383/DS90CF384 +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, +3.
DS90C383/DS90CF384 +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link—65 MHz, +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link—65 MHz General Description Features The DS90C383 transmitter converts 28 bits of LVCMOS/ LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted.
DS90C383/DS90CF384 Block Diagrams (Continued) DS90C383 DS012887-1 Order Number DS90C383MTD or DS90C383SLC See NS Package Number MTD56 or SLC64A DS90CF384 DS012887-24 Order Number DS90CF384MTD or DS90CF384SLC See NS Package Number MTD56 or SLC64A www.national.
DS90CF384MTD 12.4 mW/˚C above Maximum Package Power Dissipation Capacity 25˚C SLC64A Package: DS90C383SLC DS90CF384SLC Package Derating: DS90C383SLC 10.2 mW/˚C above DS90CF384SLC 10.2 mW/˚C above If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) −0.3V to +4V CMOS/TTL Input Voltage −0.3V to (VCC + 0.3V) CMOS/TTL Output Voltage −0.3V to (VCC + 0.
DS90C383/DS90CF384 Electrical Characteristics (Continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units TRANSMITTER SUPPLY CURRENT ICCTG Transmitter Supply Current 16 Grayscale ICCTZ (Figures 1, 3 ), TA = −40˚C to +85˚C f = 65 MHz 42 55 mA RL = 100Ω, CL = 5 pF, f = 32.5 MHz 23 35 mA 16 Grayscale Pattern f = 37.
(Continued) Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified Max Units TPLLS Symbol Transmitter Phase Lock Loop Set (Figure 11 ) Parameter Min Typ 10 ms TPDD Transmitter Power Down Delay (Figure 15 ) 100 ns Typ Max Units 2.2 5.
DS90C383/DS90CF384 AC Timing Diagrams (Continued) DS012887-4 FIGURE 2. “16 Grayscale” Test Pattern (Notes 6, 7, 8, 9) Note 6: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O. Note 7: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical stripes across the display.
DS90C383/DS90CF384 AC Timing Diagrams (Continued) DS012887-7 FIGURE 5. DS90C383 (Transmitter) Input Clock Transition Time DS012887-8 Measurements at Vdiff = 0V TCCS measured between earliest and latest LVDS edges. TxCLK Differential Low V High Edge FIGURE 6. DS90C383 (Transmitter) Channel-to-Channel Skew DS012887-9 FIGURE 7. DS90C383 (Transmitter) Setup/Hold and High/Low Times (Falling Edge Strobe) DS012887-10 FIGURE 8. DS90CF384 (Receiver) Setup/Hold and High/Low Times 7 www.national.
DS90C383/DS90CF384 AC Timing Diagrams (Continued) DS012887-11 FIGURE 9. DS90C383 (Transmitter) Clock In to Clock Out Delay (Falling Edge Strobe) DS012887-12 FIGURE 10. DS90CF384 (Receiver) Clock In to Clock Out Delay DS012887-13 FIGURE 11. DS90C383 (Transmitter) Phase Lock Loop Set Time DS012887-14 FIGURE 12. DS90CF384 (Receiver) Phase Lock Loop Set Time www.national.
DS90C383/DS90CF384 AC Timing Diagrams (Continued) DS012887-15 FIGURE 13. Seven Bits of LVDS in Once Clock Cycle DS012887-16 FIGURE 14. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs DS012887-17 FIGURE 15. Transmitter Power Down Delay 9 www.national.
DS90C383/DS90CF384 AC Timing Diagrams (Continued) DS012887-18 FIGURE 16. Receiver Power Down Delay DS012887-26 FIGURE 17. Transmitter LVDS Output Pulse Position Measurement www.national.
DS90C383/DS90CF384 AC Timing Diagrams (Continued) DS012887-25 FIGURE 18. Receiver LVDS Input Strobe Position 11 www.national.
DS90C383/DS90CF384 AC Timing Diagrams (Continued) DS012887-21 C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max Tppos — Transmitter output pulse position (min and max) RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note 10) + ISI (Inter-symbol interference) (Note 11) Cable Skew — typically 10 ps–40 ps per foot, media dependent Note 10: Cycle-to-cycle jitter is less than 250 ps at 65 MHZ Note 11: ISI is dependen
I/O No. TxIN Pin Name I 28 Description TxOUT+ O 4 Positive LVDS differentiaI data output. TxOUT− O 4 Negative LVDS differential data output. FPSHIFT IN I 1 TTL Ievel clock input. The falling edge acts as data strobe. Pin name TxCLK IN. R_FB I 1 Programmable strobe select. RTxCLK OUT+ O 1 Positive LVDS differential clock output. TxCLK OUT− O 1 Negative LVDS differential clock output. PWR DOWN I 1 TTL level input.
DS90C383/DS90CF384 DS90C383SLC SLC64A (FBGA) Package Pin Description — FPD Link Transmitter (Continued) By Pin By Pin Type A7 TxCLKOUT+ O B4 LVDS GND A8 TxOUT3+ O B7 LVDS GND G B1 TxIN1 I D5 LVDS GND G B2 TxIN0 I C6 PLL GND G B3 LVDS GND G D6 PLL GND G B4 LVDS GND G D7 PWR DWN I B5 TxOUT2- O G5 R_FB I B6 TxOUT3- O C8 TxCLKIN I B7 LVDS GND G B2 TxIN0 I B8 NC B1 TxIN1 I C1 TxIN3 D2 TxIN2 I C2 NC C1 TxIN3 I C3 NC D1 TxIN4 I C4 TxOUT1-
By Pin By Pin Type G7 TxIN21 I C7 PLL VCC P G8 TxIN23 I E1 VCC P H1 TxIN9 I E6 VCC P H2 VCC P H2 VCC P H3 TxIN11 I B8 NC H4 TxIN14 I C2 NC H5 TxIN15 I C3 NC H6 TxIN18 I F2 NC H7 TxIN19 I F3 NC H8 TxIN20 I F6 NC G : Ground I : Input O : Output P : Power NC : No Connect DS90CF384 MTD56 TSSOP Package Pin Description — FPD Link Receiver Pin Name RxIN+ I/O No. I 4 Positive LVDS differentiaI data inputs.
DS90C383/DS90CF384 DS90CF384 64 ball FBGA Package Pin Description — FPD Link Receiver (Continued) Pin Name LVDS GND I/O No. I NC Description 4 Ground pins for LVDS inputs. 6 Pins not connected.
(Continued) By Pin F2 RxOUT26 F3 NC F4 RxIN1- By Pin Type O C3 RxOUT18 O D3 RxOUT19 O I D2 RxOUT20 O F5 RxIN2+ I C1 RxOUT21 O F6 PLL GND G E1 RxOUT22 O F7 PLL VCC P F1 RxOUT23 O F8 NC E2 RxOUT24 O G1 RxOUT25 G2 NC G3 LVDS GND G G4 RxIN1+ G5 RxIN2- G6 RxIN3- G7 LVDS GND G A2 VCC P G8 PLL GND G B5 VCC P H1 RxOUT27 O D1 VCC P H2 RxIN0- I D6 VCC P O G1 RxOUT25 O F2 RxOUT26 O H1 RxOUT27 O I E4 LVDS VCC P I H4 LVDS VCC P
DS90C383/DS90CF384 Pin Diagrams for TSSOP Packages DS90CF384MTD DS90C383MTD DS012887-22 DS012887-23 TABLE 1. Programmable Transmitter Pin www.national.
DS90C383/DS90CF384 Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Molded Thin Shrink Small Outline Package, JEDEC Dimensions show in millimeters Order Number DS90C383MTD, DS90CF384MTD NS Package Number MTD56 19 www.national.
DS90C383/DS90CF384 +3.3V Programmable LVDS 24-Bit-Color Flat Panel Display (FPD) Link—65 MHz Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 64 ball, 0.
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