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DS90C387, DS90CF388

www.ti.com

SNLS012H –MAY 2000–REVISED APRIL 2013

DS90C387, DS90CF388 Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA

Check for Samples: DS90C387, DS90CF388

FEATURES

DESCRIPTION

The DS90C387/DS90CF388 transmitter/receiver pair

• Complies with OpenLDI Specification for

is designed to support dual pixel data transmission

Digital Display Interfaces

between Host and Flat Panel Display up to QXGA

• 32.5 to 112/170MHz Clock Support for

resolutions. The transmitter converts 48 bits (Dual

DS90C387, 40 to 112MHz Clock Support for

Pixel 24-bit color) of CMOS/TTL data into 8 LVDS

DS90CF388

(Low Voltage Differential Signalling) data streams.

Control signals (VSYNC, HSYNC, DE and two user-

• Supports SVGA through QXGA Panel

defined signals) are sent during blanking intervals. At

Resolutions

a maximum dual pixel rate of 112MHz, LVDS data

• Drives Long, Low Cost Cables

line speed is 672Mbps, providing a total throughput of

• Up to 5.38Gbps Bandwidth

5.38Gbps (672 Megabytes per second). Two other

modes are also supported. 24-bit color data (single

• Pre-Emphasis Reduces Cable Loading Effects

pixel) can be clocked into the transmitter at a

• DC Balance Data Transmission Provided by

maximum rate of 170MHz. In this mode, the

Transmitter Reduces ISI Distortion

transmitter provides single-to-dual pixel conversion,

• Cable Deskew of +/−1 LVDS Data Bit Time (up

and the output LVDS clock rate is 85MHz maximum.

to 80 MHz Clock Rate) of Pair-to-Pair Skew at

The third mode provides inter-operability with FPD-

Link devices.

Receiver Inputs; Intra-Pair Skew Tolerance of

300ps

The LDI chipset is improved over prior generations of

• Dual Pixel Architecture Supports Interface to

FPD-Link devices and offers higher bandwidth

GUI and Timing Controller; Optional Single support and longer cable drive with three areas of

enhancement. To increase bandwidth, the maximum

Pixel Transmitter Inputs Support Single Pixel

pixel clock rate is increased to 112 (170) MHz and 8

GUI Interface

serialized LVDS outputs are provided. Cable drive is

• Transmitter Rejects Cycle-to-Cycle Jitter

enhanced with a user selectable pre-emphasis

• 5V Tolerant on Data and Control Input Pins

feature that provides additional output current during

transitions to counteract cable loading effects. DC

• Programmable Transmitter Data and Control

balancing on a cycle-to-cycle basis, is also provided

Strobe Select (Rising or Falling Edge Strobe)

to reduce ISI (Inter-Symbol Interference). With pre-

• Backward Compatible Configuration Select

emphasis and DC balancing, a low distortion eye-

with FPD-Link

pattern is provided at the receiver end of the cable. A

• Optional Second LVDS Clock for Backward

cable deskew capability has been added to deskew

Compatibility w/ FPD-Link long cables of pair-to-pair skew of up to +/−1 LVDS

data bit time (up to 80 MHz Clock Rate). These three

• Support for Two Additional User-Defined

enhancements allow cables 5+ meters in length to be

Control Signals in DC Balanced Mode

driven. This chipset is an ideal means to solve EMI

• Compatible with ANSI/TIA/EIA-644-1995 LVDS

and cable size problems for high-resolution flat panel

Standard

applications. It provides a reliable interface based on

LVDS technology that delivers the bandwidth needed

for high-resolution panels while maximizing bit times,

and keeping clock rates low to reduce EMI and

shielding requirements. For more details, please refer

to Applications Information.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (33 pages)

PAGE 1
DS90C387, DS90CF388 www.ti.com SNLS012H – MAY 2000 – REVISED APRIL 2013 DS90C387, DS90CF388 Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA Check for Samples: DS90C387, DS90CF388 FEATURES DESCRIPTION • The DS90C387/DS90CF388 transmitter/receiver pair is designed to support dual pixel data transmission between Host and Flat Panel Display up to QXGA resolutions. The transmitter converts 48 bits (Dual Pixel 24-bit color) of CMOS/TTL data into 8 LVDS (Low Voltage Differential Signalling) data streams.
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DS90C387, DS90CF388 SNLS012H – MAY 2000 – REVISED APRIL 2013 www.ti.
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DS90C387, DS90CF388 www.ti.com SNLS012H – MAY 2000 – REVISED APRIL 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) −0.3V to +4V Supply Voltage (VCC) −0.3V to +5.5V CMOS/TTL Input Voltage −0.3V to (VCC + 0.3V) CMOS/TTL Output Voltage LVDS Receiver Input Voltage −0.3V to +3.
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DS90C387, DS90CF388 SNLS012H – MAY 2000 – REVISED APRIL 2013 www.ti.com Electrical Characteristics(1) (continued) Over recommended operating supply and temperature ranges unless otherwise specified.
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DS90C387, DS90CF388 www.ti.com SNLS012H – MAY 2000 – REVISED APRIL 2013 Electrical Characteristics(1) (continued) Over recommended operating supply and temperature ranges unless otherwise specified.
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DS90C387, DS90CF388 SNLS012H – MAY 2000 – REVISED APRIL 2013 www.ti.com Transmitter Switching Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol TPDD Parameter Min Typ Transmitter Powerdown Delay (Figure 10) Max Unit 100 ns Receiver Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified.
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DS90C387, DS90CF388 www.ti.com SNLS012H – MAY 2000 – REVISED APRIL 2013 Chipset RSKM Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified.(1) (2). See Applications Information for more details on this parameter and how to apply it. Symbol Parameter Min RSKMD Receiver Skew Margin with Deskew in DC Balance, (Figure 13) (4) f = 40 to 80 MHz 0.
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DS90C387, DS90CF388 SNLS012H – MAY 2000 – REVISED APRIL 2013 www.ti.com A. The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical stripes across the display. B. Figure 1 and Figure 2 show a falling edge data strobe (TxCLK IN/RxCLK OUT). Figure 2. “16 Grayscale” Test Pattern Figure 3. DS90C387 (Transmitter) LVDS Output Load and Transition Times Figure 4.
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DS90C387, DS90CF388 www.ti.com SNLS012H – MAY 2000 – REVISED APRIL 2013 Figure 5. DS90C387 (Transmitter) Input Clock Transition Time Figure 6. DS90C387 (Transmitter) Setup/Hold and High/Low Times (Falling Edge Strobe) Figure 7. DS90CF388 (Receiver) Setup/Hold and High/Low Times Figure 8.
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DS90C387, DS90CF388 SNLS012H – MAY 2000 – REVISED APRIL 2013 www.ti.com Figure 9. DS90CF388 (Receiver) Phase Lock Loop Set Time Figure 10. Transmitter Power Down Delay Figure 11.
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DS90C387, DS90CF388 www.ti.
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DS90C387, DS90CF388 SNLS012H – MAY 2000 – REVISED APRIL 2013 www.ti.com Figure 15.
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DS90C387, DS90CF388 www.ti.com SNLS012H – MAY 2000 – REVISED APRIL 2013 DS90C387 PIN DESCRIPTIONS — FPD LINK TRANSMITTER Pin Name I/O No. Description Rn, Gn, Bn, DE, HSYNC, VSYNC I 51 TTL level input. This includes: 16 Red, 16 Green, 16 Blue, and 3 control lines HSYNC, VSYNC, DE (Data Enable). (1) AnP O 8 Positive LVDS differential data output. AnM O 8 Negative LVDS differential data output. CLKIN I 1 TTL level clock input. R_FB I 1 Programmable data strobe select.
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DS90C387, DS90CF388 SNLS012H – MAY 2000 – REVISED APRIL 2013 www.ti.com DS90CF388 PIN DESCRIPTIONS — FPD LINK RECEIVER (continued) I/O No. Description BAL Pin Name I 1 Mode select for DC Balanced (new) or non-DC Balanced (backward compatible) interface. BAL = LOW for non-DC Balanced mode. BAL = HIGH for DC Balanced Mode (Auto-detect mode), with this pin HIGH the received LVDS clock signal is used to determine if the interface is in new or backward compatible mode.
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DS90C387, DS90CF388 www.ti.com SNLS012H – MAY 2000 – REVISED APRIL 2013 Table 2.
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DS90C387, DS90CF388 SNLS012H – MAY 2000 – REVISED APRIL 2013 www.ti.com Table 3.
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DS90C387, DS90CF388 www.ti.com SNLS012H – MAY 2000 – REVISED APRIL 2013 Table 4.
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DS90C387, DS90CF388 SNLS012H – MAY 2000 – REVISED APRIL 2013 www.ti.com NOTE: Redundant copies of certain signals are also sent. These signals are denoted with an * symbol. The DS90CF388 does not sample the bits show with an * symbol. Optional feature supported: Pre-emphasis. See Applications Information for additional details. Figure 17.
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DS90C387, DS90CF388 www.ti.com SNLS012H – MAY 2000 – REVISED APRIL 2013 NOTE: The LVDS Clock signal is also DC Balanced in this mode. The rising edge location is fixed, but the location of the falling edge will be in one of two locations as shown above. Optional features supported: Pre-emphasis, and Deskew. Figure 18. 48 Parallel TTL Data Inputs Mapped to LVDS Outputs DC Balanced Mode - Data Enabled, BAL=High Figure 19.
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DS90C387, DS90CF388 SNLS012H – MAY 2000 – REVISED APRIL 2013 www.ti.com NOTE: The control signal during blanking shown above is for R_FDE=High, when R_FDE=Low all the low/high patterns are reversed. Figure 20.
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DS90C387, DS90CF388 www.ti.com SNLS012H – MAY 2000 – REVISED APRIL 2013 APPLICATIONS INFORMATION HOW TO CONFIGURE THE DS90C387 AND DS90CF388 FOR MOST COMMON APPLICATION 1. To configure for single input pixel-to-dual pixel output application, the DS90C387 “DUAL” pin must be set to 1/2 Vcc=1.65V. This may be implemented using pull-up and pull-down resistors of 10kΩ each as shown in Figure 16. A capacitor between “DUAL” pin and ground will help to stabilize the DC voltage level in a noisy environment.
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DS90C387, DS90CF388 SNLS012H – MAY 2000 – REVISED APRIL 2013 www.ti.com Table 6. PRE-EMPHASIS NEEDED PER CABLE LENGTH (continued) Frequency PRE Voltage Typical cable length 65MHz 1.5V 10 meters 56MHz 1.0V 10 meters DC Balance In the Balanced operating modes, in addition to pixel and control information an additional bit is transmitted on every LVDS data signal line during each cycle of active data as shown in Figure 18. This bit is the DC Balance bit (DCBAL).
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DS90C387, DS90CF388 www.ti.com SNLS012H – MAY 2000 – REVISED APRIL 2013 SUPPORT OF CNTLE, CNTLF The 387/388 will also support the transmission of one or two additional user-defined control signals in the 'dual pixel' DC Balanced output mode which are active during blanking while VSYNC is low. The additional control signals, referred to as CNTLE and CNTLF, should be multiplexed with data signals and provided to the transmitter inputs. Inputs B26 - CNTLF and B27 - CNTLE are designated for this purpose.
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DS90C387, DS90CF388 SNLS012H – MAY 2000 – REVISED APRIL 2013 www.ti.com RSKMD - Receiver Skew Margin with DESKEW RSKMD is a chipset parameter and is applicable when the DESKEW feature of the DS90CF388 is employed. It is the difference between the receiver’s strobe window and the ideal pulse locations. The DESKEW feature adjusts for skew between each data channel and the clock channel. This feature is supported up to 80 MHz clock rate.
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DS90C387, DS90CF388 www.ti.com SNLS012H – MAY 2000 – REVISED APRIL 2013 Pin Diagrams Figure 21.
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DS90C387, DS90CF388 SNLS012H – MAY 2000 – REVISED APRIL 2013 www.ti.com Figure 22.
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DS90C387, DS90CF388 www.ti.com SNLS012H – MAY 2000 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision G (April 2013) to Revision H • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DS90C387VJDX/NOPB TQFP NEZ 100 1000 330.0 32.4 18.0 18.0 1.6 24.0 32.0 Q2 DS90CF388VJDX/NOPB TQFP NEZ 100 1000 330.0 32.4 18.0 18.0 1.6 24.0 32.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS90C387VJDX/NOPB TQFP NEZ 100 1000 367.0 367.0 55.0 DS90CF388VJDX/NOPB TQFP NEZ 100 1000 367.0 367.0 55.
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MECHANICAL DATA NEZ0100A PFD0100A TYPICAL VJD100A (Rev C) www.ti.
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