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DS90CF366, DS90CF386

www.ti.com

SNLS055I –NOVEMBER 1999–REVISED APRIL 2013

DS90CF386/DS90CF366 +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link - 85

MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link - 85 MHz

Check for Samples: DS90CF366, DS90CF386

FEATURES

DESCRIPTION

The DS90CF386 receiver converts the four LVDS

• 20 to 85 MHz Shift Clock Support

data streams (Up to 2.38 Gbps throughput or 297.5

• Rx Power Consumption <142 mW (typ)

Megabytes/sec bandwidth) back into parallel 28 bits

@85MHz Grayscale

of CMOS/TTL data (24 bits of RGB and 4 bits of

• Rx Power-Down Mode <1.44 mW (max)

Hsync, Vsync, DE and CNTL). Also available is the

DS90CF366 that converts the three LVDS data

• ESD Rating >7 kV (HBM), >700V (EIAJ)

streams (Up to 1.78 Gbps throughput or 223

• Supports VGA, SVGA, XGA and Single Pixel

Megabytes/sec bandwidth) back into parallel 21 bits

SXGA.

of CMOS/TTL data (18 bits of RGB and 3 bits of

• PLL Requires No External Components

Hsync, Vsync and DE). Both Receivers' outputs are

Falling edge strobe. A Rising edge or Falling edge

• Compatible with TIA/EIA-644 LVDS Standard

strobe transmitter (DS90C385/DS90C365) will

• Low Profile 56-Lead or 48-lead TSSOP

interoperate with a Falling edge strobe Receiver

Package

without any translation logic.

• DS90CF386 Also Available in a 64 Ball, 0.8mm

The DS90CF386 is also offered in a 64 ball, 0.8mm

Fine Pitch Ball Grid Array (NFBGA) Package

fine pitch ball grid array (NFBGA) package which

provides a 44 % reduction in PCB footprint compared

to the 56L TSSOP package.

This chipset is an ideal means to solve EMI and

cable size problems associated with wide, high speed

TTL interfaces.

BLOCK DIAGRAM

Figure 1. DS90CF386 Figure 2. DS90CF366

See Package Number DGG-56 (TSSOP) or See Package Number DGG-48 (TSSOP)

NZC0064A-64 (NFBGA)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (20 pages)

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DS90CF366, DS90CF386 www.ti.com SNLS055I – NOVEMBER 1999 – REVISED APRIL 2013 DS90CF386/DS90CF366 +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link - 85 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link - 85 MHz Check for Samples: DS90CF366, DS90CF386 FEATURES DESCRIPTION • • The DS90CF386 receiver converts the four LVDS data streams (Up to 2.38 Gbps throughput or 297.
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DS90CF366, DS90CF386 SNLS055I – NOVEMBER 1999 – REVISED APRIL 2013 www.ti.com Absolute Maximum Ratings (1) (2) −0.3V to +4V Supply Voltage (VCC) CMOS/TTL Output Voltage −0.3V to (VCC + 0.3V) LVDS Receiver Input Voltage −0.3V to (VCC + 0.
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DS90CF366, DS90CF386 www.ti.com SNLS055I – NOVEMBER 1999 – REVISED APRIL 2013 Electrical Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified(1) Symbol Parameter Conditions Min Typ Max Units f = 32.5 MHz 49 70 mA f = 37.5 MHz 53 75 mA f = 65 MHz 81 114 mA f = 85 MHz 96 135 mA f = 32.5 MHz 49 60 mA f = 37.5 MHz 53 65 mA f = 65 MHz 78 100 mA f = 85 MHz 90 115 mA f = 32.5 MHz 28 45 mA f = 37.
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DS90CF366, DS90CF386 SNLS055I – NOVEMBER 1999 – REVISED APRIL 2013 www.ti.com AC Timing Diagrams Figure 3. “Worst Case” Test Pattern (1) The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O. (2) The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical stripes across the display.
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DS90CF366, DS90CF386 www.ti.
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DS90CF366, DS90CF386 SNLS055I – NOVEMBER 1999 – REVISED APRIL 2013 www.ti.com Figure 8. DS90CF386/DS90CF366 (Receiver) Clock In to Clock Out Delay Figure 9. DS90CF386/DS90CF366 (Receiver) Phase Lock Loop Set Time Figure 10. 28 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90CF386 Figure 11.
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DS90CF366, DS90CF386 www.ti.com SNLS055I – NOVEMBER 1999 – REVISED APRIL 2013 Figure 12. DS90CF386/DS90CF366 (Receiver) Power Down Delay Figure 13.
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DS90CF366, DS90CF386 SNLS055I – NOVEMBER 1999 – REVISED APRIL 2013 www.ti.com Figure 14.
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DS90CF366, DS90CF386 www.ti.com SNLS055I – NOVEMBER 1999 – REVISED APRIL 2013 DS90CF386 DGG0056A Package PIN DESCRIPTIONS—24-Bit FPD Link Receiver Pin Name I/O No. Description RxIN+ I 4 Positive LVDS differentiaI data inputs. RxIN− I 4 Negative LVDS differential data inputs. RxOUT O 28 TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 3 control lines—FPLINE, FPFRAME, DRDY (also referred to as HSYNC, VSYNC, Data Enable).
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DS90CF366, DS90CF386 SNLS055I – NOVEMBER 1999 – REVISED APRIL 2013 www.ti.com DS90CF386 — 64 ball NFBGA package PIN DESCRIPTIONS — FPD Link Receiver Pin Name I/O No. RxIN+ I 4 Positive LVDS differentiaI data inputs. RxIN− I 4 Negative LVDS differential data inputs. RxOUT O 28 TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines—FPLINE, FPFRAME, DRDY (also referred to as HSYNC, VSYNC, Data Enable). RxCLK IN+ I 1 Positive LVDS differential clock input.
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DS90CF366, DS90CF386 www.ti.
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DS90CF366, DS90CF386 SNLS055I – NOVEMBER 1999 – REVISED APRIL 2013 www.ti.com Pin Diagrams for TSSOP Packages Figure 16. DS90CF386MTD Figure 17. DS90CF366MTD APPLICATIONS INFORMATION POWER SEQUENCING AND POWERDOWN MODE Outputs of the transmitter remain in TRI-STATE until the power supply reaches 2V. Clock and data outputs will begin to toggle 10 ms after VCC has reached 3V and the Powerdown pin is above 1.5V.
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DS90CF366, DS90CF386 www.ti.com SNLS055I – NOVEMBER 1999 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision H (April 2013) to Revision I • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com (4) 1-Nov-2013 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DS90CF366MTDX/NOPB TSSOP DGG 48 1000 330.0 24.4 8.6 13.2 1.6 12.0 24.0 Q1 DS90CF386MTDX/NOPB TSSOP DGG 56 1000 330.0 24.4 8.6 14.5 1.8 12.0 24.0 Q1 DS90CF386SLCX/NOPB NFBGA NZC 64 2000 330.0 16.4 8.3 8.3 2.3 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS90CF366MTDX/NOPB TSSOP DGG 48 1000 367.0 367.0 45.0 DS90CF386MTDX/NOPB TSSOP DGG 56 1000 367.0 367.0 45.0 DS90CF386SLCX/NOPB NFBGA NZC 64 2000 367.0 367.0 38.
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MECHANICAL DATA NZC0064A SLC64A (Rev C) www.ti.
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MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.