Datasheet

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DS90CF364A, DS90CF384A

www.ti.com

SNLS040I –JUNE 2000–REVISED APRIL 2013

DS90CF384A/DS90CF364A +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link - 65

MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link - 65 MHz

Check for Samples: DS90CF364A, DS90CF384A

FEATURES

DESCRIPTION

The DS90CF384A receiver converts the four LVDS

• 20 to 65 MHz Shift Clock Support

data streams (Up to 1.8 Gbps throughput or 227

• 50% Duty Cycle on Receiver Output Clock

Megabytes/sec bandwidth) back into parallel 28 bits

• Best-in-Class Set & Hold Times on

of CMOS/TTL data (24 bits of RGB and 4 bits of

RxOUTPUTs

Hsync, Vsync, DE and CNTL). Also available is the

DS90CF364A that converts the three LVDS data

• Rx Power Consumption <142 mW (typ)

streams (Up to 1.3 Gbps throughput or 170

@65MHz Grayscale

Megabytes/sec bandwidth) back into parallel 21 bits

• Rx Power-down Mode <200μW (max)

of CMOS/TTL data (18 bits of RGB and 3 bits of

• ESD Rating >7 kV (HBM), >700V (EIAJ)

Hsync, Vsync and DE). Both Receivers' outputs are

Falling edge strobe. A Rising edge or Falling edge

• Supports VGA, SVGA, XGA and Dual Pixel

strobe transmitter (DS90C383A/DS90C363A) will

SXGA.

interoperate with a Falling edge strobe Receiver

• PLL Requires no External Components

without any translation logic.

• Compatible with TIA/EIA-644 LVDS Standard

The DS90CF384A / DS90CF364A devices are

• Low Profile 56-lead or 48-lead Packages

enhanced over prior generation receivers and

provided a wider data valid time on the receiver

output.

This chipset is an ideal means to solve EMI and

cable size problems associated with wide, high speed

TTL interfaces.

BLOCK DIAGRAMS

Figure 1. DS90CF384A Figure 2. DS90CF364A

DGG-56 (TSSOP) DGG-48 (TSSOP)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (19 pages)

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DS90CF364A, DS90CF384A www.ti.com SNLS040I – JUNE 2000 – REVISED APRIL 2013 DS90CF384A/DS90CF364A +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link - 65 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link - 65 MHz Check for Samples: DS90CF364A, DS90CF384A FEATURES DESCRIPTION • • • The DS90CF384A receiver converts the four LVDS data streams (Up to 1.
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DS90CF364A, DS90CF384A SNLS040I – JUNE 2000 – REVISED APRIL 2013 www.ti.com Absolute Maximum Ratings (1) (2) −0.3V to +4V Supply Voltage (VCC) CMOS/TTL Input Voltage −0.3V to (VCC + 0.3V) CMOS/TTL Output Voltage −0.3V to (VCC + 0.3V) LVDS Receiver Input Voltage −0.3V to (VCC + 0.
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DS90CF364A, DS90CF384A www.ti.com SNLS040I – JUNE 2000 – REVISED APRIL 2013 Electrical Characteristics(1) (continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units +100 mV LVDS RECEIVER DC SPECIFICATIONS VTH Differential Input High Threshold VTL Differential Input Low Threshold IIN Input Current V CM = +1.2V −100 mV V IN = +2.4V, VCC = 3.6V ±10 μA V IN = 0V, VCC = 3.
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DS90CF364A, DS90CF384A SNLS040I – JUNE 2000 – REVISED APRIL 2013 www.ti.com Receiver Switching Characteristics(1) (continued) Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter RCOP RxCLK OUT Period (Figure 7) RCOH RxCLK OUT High Time (Figure 7) RCOL Min Typ Max Units 15 T 50 ns 5.0 7.6 9.0 ns RxCLK OUT Low Time (Figure 7) 5.0 6.3 9.0 ns RSRC RxOUT Setup to RxCLK OUT (Figure 7) 4.5 7.
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DS90CF364A, DS90CF384A www.ti.com SNLS040I – JUNE 2000 – REVISED APRIL 2013 (1) The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O. (2) The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical stripes across the display. (3) Figure 3 and Figure 5 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
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DS90CF364A, DS90CF384A SNLS040I – JUNE 2000 – REVISED APRIL 2013 Device Pin Name Signal TxCLK IN / RxCLK OUT Dot Clk www.ti.
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DS90CF364A, DS90CF384A www.ti.com SNLS040I – JUNE 2000 – REVISED APRIL 2013 Figure 6. DS90CF384A/DS90CF364A (Receiver) CMOS/TTL Output Load and Transition Times Figure 7. DS90CF384A/DS90CF364A (Receiver) Setup/Hold and High/Low Times Figure 8. DS90CF384A/DS90CF364A (Receiver) Clock In to Clock Out Delay Figure 9.
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DS90CF364A, DS90CF384A SNLS040I – JUNE 2000 – REVISED APRIL 2013 www.ti.com Figure 10. 28 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90CF384A Figure 11. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90CF364A Figure 12.
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DS90CF364A, DS90CF384A www.ti.com SNLS040I – JUNE 2000 – REVISED APRIL 2013 Figure 13.
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DS90CF364A, DS90CF384A SNLS040I – JUNE 2000 – REVISED APRIL 2013 www.ti.com Figure 14.
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DS90CF364A, DS90CF384A www.ti.com SNLS040I – JUNE 2000 – REVISED APRIL 2013 DS90CF384A PIN DESCRIPTIONS — 56 Lead TSSOP Package — 24-Bit FPD Link Receiver Pin Name I/O No. Description RxIN+ I 4 Positive LVDS differentiaI data inputs. RxIN− I 4 Negative LVDS differential data inputs. RxOUT O 28 TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 3 control lines—FPLINE, FPFRAME, DRDY (also referred to as HSYNC, VSYNC, Data Enable).
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DS90CF364A, DS90CF384A SNLS040I – JUNE 2000 – REVISED APRIL 2013 www.ti.com Pin Diagram for TSSOP Packages Figure 16. DS90CF384A DGG-56 Package 12 Submit Documentation Feedback Figure 17.
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DS90CF364A, DS90CF384A www.ti.com SNLS040I – JUNE 2000 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision H (April 2013) to Revision I • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device DS90CF364AMTDX Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TSSOP DGG 48 1000 330.0 24.4 8.6 13.2 1.6 12.0 24.0 Q1 DS90CF364AMTDX/NOP B TSSOP DGG 48 1000 330.0 24.4 8.6 13.2 1.6 12.0 24.0 Q1 DS90CF384AMTDX/NOP B TSSOP DGG 56 1000 330.0 24.4 8.6 14.5 1.8 12.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS90CF364AMTDX TSSOP DGG 48 1000 367.0 367.0 45.0 DS90CF364AMTDX/NOPB TSSOP DGG 48 1000 367.0 367.0 45.0 DS90CF384AMTDX/NOPB TSSOP DGG 56 1000 367.0 367.0 45.
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MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.