DS90C387A,DS90CF388A DS90C387A/DS90CF388A Dual Pixel LVDS Display Interface / FPD-Link Literature Number: SNLS065D
DS90C387A/DS90CF388A Dual Pixel LVDS Display Interface / FPD-Link General Description The DS90C387A/DS90CF388A transmitter/receiver pair is designed to support dual pixel data transmission between Host and Flat Panel Display up to QXGA resolutions. The transmitter converts 48 bits (Dual Pixel 24-bit color) of CMOS/TTL data and 3 control bits into 8 LVDS (Low Voltage Differential Signalling) data streams.
DS90C387A/DS90CF388A Generalized Receiver Block Diagram 10132003 Generalized Block Diagrams 10132001 www.national.
Package Derating: If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) CMOS/TTL Output Voltage 18.2mW/˚C above +25˚C DS90CF388 A 18.2mW/˚C above +25˚C ESD Rating: −0.3V to +4V CMOS/TTL Input Voltage DS90C387 A DS90C387A −0.3V to +5.5V > 6 kV > 300 V (HBM, 1.5kΩ, 100pF) (EIAJ, 0Ω, 200pF) −0.3V to (VCC + 0.3V) DS90CF388A LVDS Receiver Input Voltage −0.3V to +3.
DS90C387A/DS90CF388A Electrical Characteristics (Continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units 115 160 mA 145 200 mA 165 230 mA 210 260 mA f = 32.5 MHz 92 140 mA f = 65 MHz 100 150 mA f = 85 MHz 110 170 mA f = 112 MHz 130 190 mA 4.
Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter TCIT TxCLK IN Transition Time (Figure 5) TCIP TxCLK IN Period (Figure 6) DUAL=Gnd or Vcc DUAL=1/2Vcc Min Typ Max Units 1.0 2.0 3.0 ns ns 1.0 1.5 1.7 DUAL=Gnd or Vcc 8.928 T 30.77 ns DUAL=1/2Vcc 5.88 15.38 ns ns TCIH TxCLK in High Time (Figure 6) 0.35T 0.5T 0.65T TCIL TxCLK in Low Time (Figure 6) 0.35T 0.5T 0.65T ns TXIT TxIN Transition Time 6.0 ns 1.
DS90C387A/DS90CF388A Receiver Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Typ Max Units CLHT CMOS/TTL Low-to-High Transition Time (Figure 4), Rx data out Parameter 1.52 2.0 ns CMOS/TTL Low-to-High Transition Time (Figure 4), Rx clock out 0.5 1.0 ns CHLT CMOS/TTL High-to-Low Transition Time (Figure 4), Rx data out 1.7 2.0 ns CMOS/TTL High-to-Low Transition Time (Figure 4), Rx clock out 0.5 1.0 ns T 30.
DS90C387A/DS90CF388A AC Timing Diagrams 10132010 FIGURE 1. “Worst Case” Test Pattern 10132011 FIGURE 2. “16 Grayscale” Test Pattern (Notes 7, 8, 9) Note 7: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O. Note 8: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical stripes across the display.
DS90C387A/DS90CF388A AC Timing Diagrams (Continued) 10132012 FIGURE 3. DS90C387A (Transmitter) LVDS Output Load and Transition Times 10132013 FIGURE 4. DS90CF388A (Receiver) CMOS/TTL Output Load and Transition Times 10132014 FIGURE 5. DS90C387A (Transmitter) Input Clock Transition Time 10132015 FIGURE 6. DS90C387A (Transmitter) Setup/Hold and High/Low Times (Falling Edge Strobe) www.national.
DS90C387A/DS90CF388A AC Timing Diagrams (Continued) 10132016 FIGURE 7. DS90CF388A (Receiver) Setup/Hold and High/Low Times 10132019 FIGURE 8. DS90C387A (Transmitter) Phase Lock Loop Set Time 10132020 FIGURE 9. DS90CF388A (Receiver) Phase Lock Loop Set Time 9 www.national.
DS90C387A/DS90CF388A AC Timing Diagrams (Continued) 10132021 FIGURE 10. Transmitter Power Down Delay 10132022 FIGURE 11.
DS90C387A/DS90CF388A AC Timing Diagrams (Continued) 10132027 FIGURE 13. TJCC Test Setup - DS90C387A 10132028 FIGURE 14. Timing Diagram of the Input Cycle-to-Cycle Clock Jitter 11 www.national.
DS90C387A/DS90CF388A DS90C387A Pin Descriptions — FPD Link Transmitter Pin Name I/O No. Description Rn, Gn, Bn, DE, HSYNC, VSYNC I 51 TTL level input. This includes: 16 Red, 16 Green, 16 Blue, and 3 control lines HSYNC, VSYNC, DE (Data Enable).(Note 10) AnP O 8 Positive LVDS differential data output. AnM O 8 Negative LVDS differential data output. CLKIN I 1 TTL level clock input. R_FB I 1 Programmable data strobe select. Rising data strobe edge selected when input is high.
Pin Name I/O No. Description AnP I 8 AnM I 8 Negative LVDS differential data inputs. Rn, Gn, Bn, DE, HSYNC, VSYNC O 51 TTL level data outputs. This includes: 16 Red, 16 Green, 16 Blue, and 3 control lines — HSYNC (LP), VSYNC (FLM), DE (Data Enable). RxCLK INP I 1 Positive LVDS differential clock input. RxCLK INM I 1 Negative LVDS differential clock input. RxCLK OUT O 1 TTL level clock output. The falling edge acts as data strobe.
DS90C387A/DS90CF388A LVDS Interface / TFT Data (Color) Mapping Different color mapping options exist. See National Application Notes 1127 and 1163 for details. only. Also, the DE signal is mapped to two LVDS sub symbols. The DS90CF388A only samples the DE bit on channel A2. Two FPD-Link receivers may also be used in place of the DS90CF388A, since the DS90C387A provides two LVDS clocks. If this is the case, the FPD-Link receiver datasheet needs to be consulted for recovery mapping information.
HOW TO CONFIGURE THE DS90C387A AND DS90CF388A FOR MOST COMMON APPLICATION TRANSMITTER FEATURES The transmitter is designed to reject cycle-to-cycle jitter which may be seen at the transmitter input clock. Very low cycle-to-cycle jitter is passed on to the transmitter outputs. This significantly reduces the impact of jitter provided by the input clock source, and improves the accuracy of data sampling.
DS90C387A/DS90CF388A Applications Information cycle-to-cycle basis, is also provided to reduce ISI (InterSymbol Interference). With pre-emphasis and DC balancing, a low distortion eye-pattern is provided at the receiver end of the cable. A cable deskew capability has been added to deskew long cables of pair-to-pair skew of up to +/−1 LVDS data bit time (up to 80 MHz Clock Rate). These three enhancements allow cables 5+ meters in length to be driven depending upon media and clock rate.
DS90C387A/DS90CF388A Pin Diagram Transmitter-DS90C387A 10132006 17 www.national.
DS90C387A/DS90CF388A Pin Diagram Receiver-DS90CF388A 10132007 www.national.
inches (millimeters) unless otherwise noted Dimensions show in millimeters Order Number DS90C387AVJD and DS90CF388AVJD NS Package Number VJD100A National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com.
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
