Datasheet

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DS90CR216A, DS90CR286A

www.ti.com

SNLS043F –MAY 2000–REVISED FEBRUARY 2013

DS90CR286A/DS90CR286AQ/DS90CR216A +3.3V Rising Edge Data Strobe LVDS Receiver

28-Bit Channel Link - 66 MHz, +3.3V Rising Edge Strobe LVDS Receiver 21-Bit Channel

Link - 66 MHz

Check for Samples: DS90CR216A, DS90CR286A

FEATURES

DESCRIPTION

The DS90CR286A receiver converts the four LVDS

• 20 to 66 MHz Shift Clock Support

data streams (Up to 1.848 Gbps throughput or 231

• 50% Duty Cycle on Receiver Output Clock

Megabytes/sec bandwidth) back into parallel 28 bits

• Best–in–Class Set & Hold Times on

of CMOS/TTL data. Also available is the

RxOUTPUTs

DS90CR216A that converts the three LVDS data

streams (Up to 1.386 Gbps throughput or 173

• Rx Power Consumption <270 mW (typ)

Megabytes/sec bandwidth) back into parallel 21 bits

@66MHz Worst Case

of CMOS/TTL data. Both Receivers' outputs are

• Rx Power-down Mode <200μW (max)

Rising edge strobe.

• ESD Rating >7 kV (HBM), >700V (EIAJ)

Both devices are offered in TSSOP packages.

• PLL Requires No External Components

The DS90CR286A / DS90CR216A devices are

• Compatible with TIA/EIA-644 LVDS Standard

enhanced over prior generation receivers and

• Low Profile 56-Lead or 48-Lead TSSOP

provided a wider data valid time on the receiver

Package

output.

• Operating Temperature: −40°C to +85°C

This chipset is an ideal means to solve EMI and

• Automotive Q grade available - AEC-Q100

cable size problems associated with wide, high speed

TTL interfaces.

Grade 3 Qualified

BLOCK DIAGRAM

Figure 1. DS90CR286A Figure 2. DS90CR216A

See Package Number DGG-56 (TSSOP) See Package Number DGG-48 (TSSOP)

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (17 pages)

PAGE 1
DS90CR216A, DS90CR286A www.ti.com SNLS043F – MAY 2000 – REVISED FEBRUARY 2013 DS90CR286A/DS90CR286AQ/DS90CR216A +3.3V Rising Edge Data Strobe LVDS Receiver 28-Bit Channel Link - 66 MHz, +3.3V Rising Edge Strobe LVDS Receiver 21-Bit Channel Link - 66 MHz Check for Samples: DS90CR216A, DS90CR286A FEATURES DESCRIPTION • • • The DS90CR286A receiver converts the four LVDS data streams (Up to 1.848 Gbps throughput or 231 Megabytes/sec bandwidth) back into parallel 28 bits of CMOS/TTL data.
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DS90CR216A, DS90CR286A SNLS043F – MAY 2000 – REVISED FEBRUARY 2013 www.ti.com Absolute Maximum Ratings (1) (2) −0.3V to +4V Supply Voltage (VCC) CMOS/TTL Output Voltage −0.3V to (VCC + 0.3V) LVDS Receiver Input Voltage −0.3V to (VCC + 0.3V) Junction Temperature +150°C Storage Temperature −65°C to +150°C Lead Temperature (Soldering, 4 sec) Maximum Package Power Dissipation Capacity @ 25°C +260°C DGG0056A (TSSOP) Package DS90CR286AMTD DGG0048A (TSSOP) Package DS90CR216AMTD 1.
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DS90CR216A, DS90CR286A www.ti.com SNLS043F – MAY 2000 – REVISED FEBRUARY 2013 Electrical Characteristics(1)(2) (continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units RECEIVER SUPPLY CURRENT ICCRW CL = 8 pF, Worst Case Pattern, DS90CR286A (Figure 3 Figure 4), TA=−10°C to +70°C f = 33 MHz 49 65 mA f = 37.
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DS90CR216A, DS90CR286A SNLS043F – MAY 2000 – REVISED FEBRUARY 2013 www.ti.com Receiver Switching Characteristics(1) (continued) Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter f = 66 MHz Min Typ Max Units RCOH RxCLK OUT High Time (Figure 5) 5.0 7.6 ns RCOL RxCLK OUT Low Time (Figure 5) 5.0 6.3 ns RSRC RxOUT Setup to RxCLK OUT (Figure 5) 4.5 7.3 ns RHRC RxOUT Hold to RxCLK OUT (Figure 5) 4.0 6.3 ns 3.5 5.
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DS90CR216A, DS90CR286A www.ti.com SNLS043F – MAY 2000 – REVISED FEBRUARY 2013 Figure 6. DS90CR286A/DS90CR216A (Receiver) Clock In to Clock Out Delay Figure 7. DS90CR286A/DS90CR216A (Receiver) Phase Lock Loop Set Time Figure 8.
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DS90CR216A, DS90CR286A SNLS043F – MAY 2000 – REVISED FEBRUARY 2013 www.ti.com Figure 9. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90CR216A Figure 10.
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DS90CR216A, DS90CR286A www.ti.com SNLS043F – MAY 2000 – REVISED FEBRUARY 2013 Figure 11.
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DS90CR216A, DS90CR286A SNLS043F – MAY 2000 – REVISED FEBRUARY 2013 www.ti.com Figure 12.
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DS90CR216A, DS90CR286A www.ti.
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DS90CR216A, DS90CR286A SNLS043F – MAY 2000 – REVISED FEBRUARY 2013 www.ti.com DS90CR216A PIN DESCRIPTIONS — DGG0048A Package — 21-Bit Channel Link Receiver (continued) I/O No. PLL GND Pin Name I 2 Ground pin for PLL. Description LVDS V CC I 1 Power supply pin for LVDS inputs. LVDS GND I 3 Ground pins for LVDS inputs. Pin Diagram for TSSOP Packages Figure 14. DS90CR286AMTD Figure 15.
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DS90CR216A, DS90CR286A www.ti.com SNLS043F – MAY 2000 – REVISED FEBRUARY 2013 REVISION HISTORY Changes from Revision E (February 2013) to Revision F • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com (4) 1-Nov-2013 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DS90CR216AMTDX/NOP B TSSOP DGG 48 1000 330.0 24.4 8.6 13.2 1.6 12.0 24.0 Q1 DS90CR286AMTDX/NOP B TSSOP DGG 56 1000 330.0 24.4 8.6 14.5 1.8 12.0 24.0 Q1 DS90CR286AQMTX/NOP B TSSOP DGG 56 1000 330.0 24.4 8.6 14.5 1.8 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS90CR216AMTDX/NOPB TSSOP DGG 48 1000 367.0 367.0 45.0 DS90CR286AMTDX/NOPB TSSOP DGG 56 1000 367.0 367.0 45.0 DS90CR286AQMTX/NOP B TSSOP DGG 56 1000 367.0 367.0 45.
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MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
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