Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - customised TSSOP 56

DS90CR287, DS90CR288A

www.ti.com

SNLS056G –OCTOBER 1999–REVISED MARCH 2013

DS90CR287/DS90CR288A +3.3V Rising Edge Data Strobe LVDS

28-Bit Channel Link - 85MHz

Check for Samples: DS90CR287, DS90CR288A

FEATURES

DESCRIPTION

The DS90CR287 transmitter converts 28 bits of

• 20 to 85 MHz Shift Clock Support

LVCMOS/LVTTL data into four LVDS (Low Voltage

• 50% Duty Cycle on Receiver Output Clock

Differential Signaling) data streams. A phase-locked

• 2.5 / 0 ns Set & Hold Times on TxINPUTs

transmit clock is transmitted in parallel with the data

streams over a fifth LVDS link. Every cycle of the

• Low Power Consumption

transmit clock 28 bits of input data are sampled and

• ±1V Common-Mode Range (around +1.2V)

transmitted.

• Narrow Bus Reduces Cable Size and Cost

The DS90CR288A receiver converts the four LVDS

• Up to 2.38 Gbps Throughput

data streams back into 28 bits of LVCMOS/LVTTL

• Up to 297.5 Mbytes/sec Bandwidth

data. At a transmit clock frequency of 85 MHz, 28 bits

of TTL data are transmitted at a rate of 595 Mbps per

• 345 mV (typ) Swing LVDS Devices for Low EMI

LVDS data channel. Using a 85 MHz clock, the data

• PLL Requires no External Components

throughput is 2.38 Gbit/s (297.5 Mbytes/sec).

• Rising Edge Data Strobe

This chipset is an ideal means to solve EMI and

• Compatible with TIA/EIA-644 LVDS Standard

cable size problems associated with wide, high-speed

• Low Profile 56-Lead TSSOP Package

TTL interfaces.

Block Diagram

Figure 1. DS90CR287 Figure 2. DS90CR288A

See Package Number DGG-56 (TSSOP) See Package Number DGG-56 (TSSOP)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (24 pages)

PAGE 1
DS90CR287, DS90CR288A www.ti.com SNLS056G – OCTOBER 1999 – REVISED MARCH 2013 DS90CR287/DS90CR288A +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link - 85MHz Check for Samples: DS90CR287, DS90CR288A FEATURES DESCRIPTION • • • • • • • • • • • • • The DS90CR287 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link.
PAGE 2
DS90CR287, DS90CR288A SNLS056G – OCTOBER 1999 – REVISED MARCH 2013 www.ti.com Pin Diagram for TSSOP Packages Figure 3. DS90CR287 Figure 4. DS90CR288A Typical Application Figure 5. DS90CR288A These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
PAGE 3
DS90CR287, DS90CR288A www.ti.com SNLS056G – OCTOBER 1999 – REVISED MARCH 2013 Absolute Maximum Ratings (1) (2) −0.3V to +4V Supply Voltage (VCC) CMOS/TTL Input Voltage −0.5V to (VCC + 0.3V) CMOS/TTL Output Voltage −0.3V to (VCC + 0.3V) LVDS Receiver Input Voltage −0.3V to (VCC + 0.3V) LVDS Driver Output Voltage −0.3V to (VCC + 0.3V) LVDS Output Short Circuit Duration Continuous Junction Temperature +150°C Storage Temperature −65°C to +150°C Lead Temperature (Soldering, 4 sec.
PAGE 4
DS90CR287, DS90CR288A SNLS056G – OCTOBER 1999 – REVISED MARCH 2013 www.ti.com Electrical Characteristics (1) Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter Conditions Min Typ (2) Max Units LVCMOS/LVTTL DC SPECIFICATIONS VIH High Level Input Voltage 2.0 VCC V VIL Low Level Input Voltage GND 0.8 V VOH High Level Output Voltage IOH = −0.4 mA VOL Low Level Output Voltage IOL = 2 mA 0.06 0.
PAGE 5
DS90CR287, DS90CR288A www.ti.com SNLS056G – OCTOBER 1999 – REVISED MARCH 2013 Transmitter Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter Min Typ (1) Max Units LLHT LVDS Low-to-High Transition Time Figure 7 0.75 1.5 ns LHLT LVDS High-to-Low Transition Time Figure 7 0.75 1.5 ns TCIT TxCLK IN Transition Time Figure 9 6.0 ns TPPos0 Transmitter Output Pulse Position for Bit0 Figure 19 TPPos1 TPPos2 1.0 −0.
PAGE 6
DS90CR287, DS90CR288A SNLS056G – OCTOBER 1999 – REVISED MARCH 2013 www.ti.com Receiver Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter Min Typ (1) Max Units CLHT CMOS/TTL Low-to-High Transition Time Figure 8 2 3.5 ns CHLT CMOS/TTL High-to-Low Transition Time Figure 8 1.8 3.5 ns RSPos0 Receiver Input Strobe Position for Bit 0 Figure 20 0.49 0.84 1.19 ns RSPos1 Receiver Input Strobe Position for Bit 1 2.
PAGE 7
DS90CR287, DS90CR288A www.ti.com SNLS056G – OCTOBER 1999 – REVISED MARCH 2013 AC Timing Diagrams Figure 6. “Worst Case” Test Pattern Figure 7. DS90CR287 (Transmitter) LVDS Output Load and Transition Times Figure 8. DS90CR288A (Receiver) CMOS/TTL Output Load and Transition Times Figure 9.
PAGE 8
DS90CR287, DS90CR288A SNLS056G – OCTOBER 1999 – REVISED MARCH 2013 www.ti.com Figure 10. DS90CR287 (Transmitter) Setup/Hold and High/Low Times Figure 11. DS90CR288A (Receiver) Setup/Hold and High/Low Times Figure 12. DS90CR287 (Transmitter) Clock In to Clock Out Delay Figure 13.
PAGE 9
DS90CR287, DS90CR288A www.ti.com SNLS056G – OCTOBER 1999 – REVISED MARCH 2013 Figure 14. DS90CR287 (Transmitter) Phase Lock Loop Set Time Figure 15. DS90CR288A (Receiver) Phase Lock Loop Set Time Figure 16.
PAGE 10
DS90CR287, DS90CR288A SNLS056G – OCTOBER 1999 – REVISED MARCH 2013 www.ti.com Figure 17. Transmitter Powerdown Delay Figure 18. Receiver Powerdown Delay Figure 19.
PAGE 11
DS90CR287, DS90CR288A www.ti.com SNLS056G – OCTOBER 1999 – REVISED MARCH 2013 Figure 20.
PAGE 12
DS90CR287, DS90CR288A SNLS056G – OCTOBER 1999 – REVISED MARCH 2013 www.ti.com DS90CR287 DGG (TSSOP) Package PIN DESCRIPTION — Channel Link Transmitter Pin Name I/O No. Description TxIN I 28 TTL level input. TxOUT+ O 4 Positive LVDS differential data output. TxOUT− O 4 Negative LVDS differential data output. TxCLK IN I 1 TTL level clock input. The rising edge acts as data strobe. Pin name TxCLK IN. See APPLICATIONS INFORMATION section.
PAGE 13
DS90CR287, DS90CR288A www.ti.com SNLS056G – OCTOBER 1999 – REVISED MARCH 2013 APPLICATIONS INFORMATION The TSSOP version of the DS90CR287 and DS90CR288A are backward compatible with the existing 5V Channel Link transmitter/receiver pair (DS90CR283, DS90CR284). To upgrade from a 5V to a 3.3V system the following must be addressed: 1. Change 5V power supply to 3.3V. Provide this supply to the VCC, LVDS VCC and PLL VCC. 2. Transmitter input and control inputs except 3.3V TTL/CMOS levels.
PAGE 14
DS90CR287, DS90CR288A SNLS056G – OCTOBER 1999 – REVISED MARCH 2013 www.ti.com line of the differential pair. Care should be taken to ensure that the differential trace impedance match the differential impedance of the selected physical media (this impedance should also match the value of the termination resistor that is connected across the differential pair at the receiver's input).
PAGE 15
DS90CR287, DS90CR288A www.ti.com SNLS056G – OCTOBER 1999 – REVISED MARCH 2013 CLOCK JITTER: The CHANNEL LINK devices employ a PLL to generate and recover the clock transmitted across the LVDS interface. The width of each bit in the serialized LVDS data stream is one-seventh the clock period. For example, a 85 MHz clock has a period of 11.76 ns which results in a data bit width of 1.68 ns.
PAGE 16
DS90CR287, DS90CR288A SNLS056G – OCTOBER 1999 – REVISED MARCH 2013 www.ti.com Figure 24.
PAGE 17
DS90CR287, DS90CR288A www.ti.com SNLS056G – OCTOBER 1999 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision F (March 2013) to Revision G • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
PAGE 18
PACKAGE OPTION ADDENDUM www.ti.
PAGE 19
PACKAGE OPTION ADDENDUM www.ti.com (4) 26-Nov-2013 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
PAGE 20
PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing DS90CR287MTDX/NOPB TSSOP DS90CR288AMTDX DS90CR288AMTDX/NOP B SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DGG 56 1000 330.0 24.4 8.6 14.5 1.8 12.0 24.0 Q1 TSSOP DGG 56 1000 330.0 24.4 8.6 14.5 1.8 12.0 24.0 Q1 TSSOP DGG 56 1000 330.0 24.4 8.6 14.5 1.8 12.0 24.
PAGE 21
PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS90CR287MTDX/NOPB TSSOP DGG 56 1000 367.0 367.0 45.0 DS90CR288AMTDX TSSOP DGG 56 1000 367.0 367.0 45.0 DS90CR288AMTDX/NOPB TSSOP DGG 56 1000 367.0 367.0 45.
PAGE 22
MECHANICAL DATA NZC0064A SLC64A (Rev C) www.ti.
PAGE 23
MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 24
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.