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DS90LT012AQ

www.ti.com

SNLS297E –MAY 2008–REVISED APRIL 2013

DS90LT012AQ Automotive LVDS Differential Line Receiver

Check for Samples: DS90LT012AQ

FEATURES

DESCRIPTION

The DS90LT012AQ is a single CMOS differential line

• AECQ-100 Grade 1

receiver designed for applications requiring ultra low

• -40 to +125°C Temperature Range Operation

power dissipation, low noise, and high data rates.

• Compatible with ANSI TIA/EIA-644-A Standard

The devices are designed to support data rates in

excess of 400 Mbps (200 MHz) utilizing Low Voltage

• >400 Mbps (200 MHz) Switching Rates

Differential Swing (LVDS) technology

• 100 ps Differential Skew (Typical)

The DS90LT012AQ accepts low voltage (350 mV

• 3.5 ns Maximum Propagation Delay

typical) differential input signals and translates them

• Integrated Line Termination Resistor (100Ω

to 3V CMOS output levels. The DS90LT012AQ

Typical)

includes an input line termination resistor for point-to-

• Single 3.3V power supply design

point applications.

• Power Down High Impedance on LVDS Inputs

The DS90LT012AQ and companion LVDS line driver

DS90LV011AQ provide a new alternative to high

• LVDS Inputs Accept LVDS/CML/LVPECL

power PECL/ECL devices for high speed interface

Signals

applications.

• Pinout Simplifies PCB Layout

• Low Power Dissipation (10mW Typical@ 3.3V

Static)

• SOT-23 5-Lead Package

Connection Diagram

Figure 1. Top View

See Package Number DBV

Functional Diagram

Figure 2. DS90LT012AQ

Truth Table

INPUTS OUTPUT

[IN+] − [IN−] TTL OUT

≥ 0V H

≤ −0.1V L

Full Fail-safe OPEN/SHORT or Terminated H

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (13 pages)

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DS90LT012AQ www.ti.com SNLS297E – MAY 2008 – REVISED APRIL 2013 DS90LT012AQ Automotive LVDS Differential Line Receiver Check for Samples: DS90LT012AQ FEATURES DESCRIPTION • • • • • • • The DS90LT012AQ is a single CMOS differential line receiver designed for applications requiring ultra low power dissipation, low noise, and high data rates.
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DS90LT012AQ SNLS297E – MAY 2008 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) −0.3V to +4V Supply Voltage (VDD) −0.3V to +3.9V Input Voltage (IN+, IN−) −0.3V to (VDD + 0.
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DS90LT012AQ www.ti.com SNLS297E – MAY 2008 – REVISED APRIL 2013 Electrical Characteristics (continued) Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (1)(2) Symbol VOH Parameter Conditions IOH = −0.4 mA, VID = +200 mV Output High Voltage VOL Min Typ TTL OUT Units 2.4 3.1 V 2.4 3.1 V IOH = −0.4 mA, Inputs shorted 2.4 3.1 IOL = 2 mA, VID = −200 mV Output Low Voltage Max IOH = −0.4 mA, Inputs terminated 0.5 V −100 mA 9 mA −15 −50 −1.5 −0.
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DS90LT012AQ SNLS297E – MAY 2008 – REVISED APRIL 2013 www.ti.com Parameter Measurement Information (continued) Figure 4. Receiver Propagation Delay and Transition Time Waveforms Typical Applications Figure 5.
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DS90LT012AQ www.ti.com SNLS297E – MAY 2008 – REVISED APRIL 2013 POWER DECOUPLING RECOMMENDATIONS Bypass capacitors must be used on power pins. Use high frequency ceramic (surface mount is recommended) 0.1μF and 0.001μF capacitors in parallel at the power supply pin with the smallest value capacitor closest to the device supply pin. Additional scattered capacitors over the printed circuit board will improve decoupling. Multiple vias should be used to connect the decoupling capacitors to the power planes.
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DS90LT012AQ SNLS297E – MAY 2008 – REVISED APRIL 2013 www.ti.com Figure 6. VTC of the DS90LT012AQ LVDS Receiver FAIL SAFE BIASING External pull up and pull down resistors may be used to provide enough of an offset to enable an input failsafe under open-circuit conditions. This configuration ties the positive LVDS input pin to VDD thru a pull up resistor and the negative LVDS input pin is tied to GND by a pull down resistor.
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DS90LT012AQ www.ti.com SNLS297E – MAY 2008 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision D (April 2013) to Revision E • Page Changed layout of National Data Sheet to TI format ............................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing DS90LT012AQMF/NOPB SOT-23 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 DS90LT012AQMFE/NOP B SOT-23 DBV 5 250 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 DS90LT012AQMFX/NOP B SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS90LT012AQMF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 DS90LT012AQMFE/NOPB SOT-23 DBV 5 250 210.0 185.0 35.0 DS90LT012AQMFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.
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