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DS90LV001

www.ti.com

SNLS067E –JANUARY 2001–REVISED APRIL 2013

DS90LV001 800 Mbps LVDS Buffer

Check for Samples: DS90LV001

FEATURES

DESCRIPTION

The DS90LV001 LVDS-LVDS Buffer takes an LVDS

• Single +3.3 V Supply

input signal and provides an LVDS output signal. In

• LVDS Receiver Inputs Accept LVPECL Signals

many large systems, signals are distributed across

• TRI-STATE Outputs

backplanes, and one of the limiting factors for system

speed is the "stub length" or the distance between

• Receiver Input Threshold < ±100 mV

the transmission line and the unterminated receivers

• Fast Propagation Delay of 1.4 ns (Typ)

on individual cards. Although it is generally

• Low Jitter 800 Mbps Fully Differential Data

recognized that this distance should be as short as

Path

possible to maximize system performance, real-world

packaging concerns often make it difficult to make the

• 100 ps (Typ) of pk-pk Jitter with PRBS = 2

−1

stubs as short as the designer would like.

Data Pattern at 800 Mbps

The DS90LV001, available in the WSON package,

• Compatible with ANSI/TIA/EIA-644-A LVDS

will allow the receiver to be placed very close to the

Standard

main transmission line, thus improving system

• 8 pin SOIC and Space Saving (70%) WSON

performance.

Package

A wide input dynamic range will allow the

• Industrial Temperature Range

DS90LV001 to receive differential signals from

LVPECL as well as LVDS sources. This will allow the

device to also fill the role of an LVPECL-LVDS

translator.

An output enable pin is provided, which allows the

user to place the LVDS output in TRI-STATE.

The DS90LV001 is offered in two package options,

an 8 pin WSON and SOIC.

Connection Diagram

Figure 1. Top View

See Package Number D (R-PDSO-G8), NGK0008A

Block Diagram

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (21 pages)

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DS90LV001 www.ti.com SNLS067E – JANUARY 2001 – REVISED APRIL 2013 DS90LV001 800 Mbps LVDS Buffer Check for Samples: DS90LV001 FEATURES DESCRIPTION • • • • • • The DS90LV001 LVDS-LVDS Buffer takes an LVDS input signal and provides an LVDS output signal. In many large systems, signals are distributed across backplanes, and one of the limiting factors for system speed is the "stub length" or the distance between the transmission line and the unterminated receivers on individual cards.
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DS90LV001 SNLS067E – JANUARY 2001 – REVISED APRIL 2013 www.ti.com Absolute Maximum Ratings (1) −0.3V to +4V Supply Voltage (VCC) −0.3V to (VCC + 0.3V) LVCMOS/LVTTL Input Voltage (EN) LVDS Receiver Input Voltage (IN+, IN−) −0.3V to +4V LVDS Driver Output Voltage (OUT+, OUT−) −0.3V to +4V LVDS Output Short Circuit Current Continuous Junction Temperature +150°C −65°C to +150°C Storage Temperature Range Lead Temperature Range Soldering (4 sec.
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DS90LV001 www.ti.com SNLS067E – JANUARY 2001 – REVISED APRIL 2013 Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified (1) (2) Symbol Parameter Conditions Min Typ Max Units V LVCMOS/LVTTL DC SPECIFICATIONS (EN) VIH High Level Input Voltage 2.0 VCC VIL Low Level Input Voltage GND 0.8 V IIH High Level Input Current VIN = 3.6V or 2.0V, VCC = 3.6V +20 μA IIL Low Level Input Current VIN = GND or 0.8V, VCC = 3.
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DS90LV001 SNLS067E – JANUARY 2001 – REVISED APRIL 2013 www.ti.com AC Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified (1) Symbol Parameter Conditions Typ Max Units 1.0 1.4 2.0 ns 1.0 1.4 2.
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DS90LV001 www.ti.com SNLS067E – JANUARY 2001 – REVISED APRIL 2013 DC Test Circuits Figure 2. Differential Driver DC Test Circuit Figure 3. Differential Driver Full Load DC Test Circuit AC Test Circuits and Timing Diagrams Figure 4. LVDS Output Load Figure 5.
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DS90LV001 SNLS067E – JANUARY 2001 – REVISED APRIL 2013 www.ti.com Figure 6. LVDS Output Transition Time Figure 7. TRI-STATE Delay Test Circuit Figure 8.
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DS90LV001 www.ti.com SNLS067E – JANUARY 2001 – REVISED APRIL 2013 DS90LV001 Pin Descriptions (SOIC and WSON) Pin Name Pin # Input/Output Description GND 1 P Ground IN − 2 I Inverting receiver LVDS input pin IN+ 3 I Non-inverting receiver LVDS input pin NC 4 VCC 5 P No Connect Power Supply, 3.3V ± 0.3V. OUT+ 6 O Non-inverting driver LVDS output pin OUT - 7 O Inverting driver LVDS output pin EN 8 I Enable pin.
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DS90LV001 SNLS067E – JANUARY 2001 – REVISED APRIL 2013 www.ti.com APPLICATION INFORMATION MODE OF OPERATION The DS90LV001 can be used as a "stub-hider." In many systems, signals are distributed across backplanes, and one of the limiting factors for system speed is the "stub length" or the distance between the transmission line and the unterminated receivers on the individual cards.
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DS90LV001 www.ti.com SNLS067E – JANUARY 2001 – REVISED APRIL 2013 The outer layers of the PCB may be flooded with additional ground plane. These planes will improve shielding and isolation as well as increase the intrinsic capacitance of the power supply plane system. Naturally, to be effective, these planes must be tied to the ground supply plane at frequent intervals with vias.
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DS90LV001 SNLS067E – JANUARY 2001 – REVISED APRIL 2013 www.ti.com Typical Performance Curves 10 Output High Voltage vs Power Supply Voltage Output Low Voltage vs Power Supply Voltage Figure 9. Figure 10. Output Short Circuit Current vs Power Supply Voltage Differential Output Short Circuit Current vs Power Supply Voltage Figure 11. Figure 12. Output TRI-STATE Current vs Power Supply Voltage Offset Voltage vs Power Supply Voltage Figure 13. Figure 14.
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DS90LV001 www.ti.com SNLS067E – JANUARY 2001 – REVISED APRIL 2013 Typical Performance Curves (continued) Differential Output Voltage vs Power Supply Voltage Differential Output Voltage vs Load Resistor Figure 15. Figure 16. Power Supply Current vs Frequency Power Supply Current vs Power Supply Voltage Figure 17. Figure 18. TRI-STATE Power Supply Current vs Power Supply Voltage Differential Transition Voltage vs Power Supply Voltage Figure 19. Figure 20.
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DS90LV001 SNLS067E – JANUARY 2001 – REVISED APRIL 2013 www.ti.com Typical Performance Curves (continued) 12 Differential Propagation Delay vs Power Supply Voltage Differential Propagation Delay vs Ambient Temperature Figure 21. Figure 22. Differential Skew vs Power Supply Voltage Differential Skew vs Ambient Temperature Figure 23. Figure 24. Transition Time vs Power Supply Voltage Transition Time vs Ambient Temperature Figure 25. Figure 26.
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DS90LV001 www.ti.com SNLS067E – JANUARY 2001 – REVISED APRIL 2013 Typical Performance Curves (continued) Differential Propagation Delay vs Differential Input Voltage Differential Propagation Delay vs Common-Mode Voltage Figure 27. Figure 28. Peak-to-Peak Output Jitter at VCM = 0.4V vs Differential Input Voltage Peak-to-Peak Output Jitter at VCM = 2.9V vs Differential Input Voltage Figure 29. Figure 30. Peak-to-Peak Output Jitter at VCM = 1.
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DS90LV001 SNLS067E – JANUARY 2001 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision D (April 2013) to Revision E • 14 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DS90LV001TLD WSON NGK 8 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 DS90LV001TLD/NOPB WSON NGK 8 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 DS90LV001TLDX/NOPB WSON NGK 8 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS90LV001TLD WSON NGK 8 1000 210.0 185.0 35.0 DS90LV001TLD/NOPB WSON NGK 8 1000 213.0 191.0 55.0 DS90LV001TLDX/NOPB WSON NGK 8 4500 367.0 367.0 35.0 DS90LV001TMX SOIC D 8 2500 367.0 367.0 35.0 DS90LV001TMX/NOPB SOIC D 8 2500 367.0 367.0 35.
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MECHANICAL DATA NGK0008A LDA08A (Rev C) www.ti.
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