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DS90LV018A

www.ti.com

SNLS014D –JUNE 1998–REVISED APRIL 2013

DS90LV018A 3V LVDS Single CMOS Differential Line Receiver

Check for Samples: DS90LV018A

FEATURES

DESCRIPTION

The DS90LV018A is a single CMOS differential line

• >400 Mbps (200 MHz) Switching Rates

receiver designed for applications requiring ultra low

• 50 ps Differential Skew (Typical)

power dissipation, low noise and high data rates. The

• 2.5 ns Maximum Propagation Delay

device is designed to support data rates in excess of

400 Mbps (200 MHz) utilizing Low Voltage Differential

• 3.3V Power Supply Design

Signaling (LVDS) technology.

• Flow-Through Pinout

The DS90LV018A accepts low voltage (350 mV

• Power Down High Impedance on LVDS Inputs

typical) differential input signals and translates them

• Low Power Design (18mW @ 3.3V Static)

to 3V CMOS output levels. The receiver also

• Interoperable with Existing 5V LVDS Networks

supports open, shorted and terminated (100Ω) input

fail-safe. The receiver output will be HIGH for all fail-

• Accepts Small Swing (350 mV Typical)

safe conditions. The DS90LV018A has a flow-through

Differential Signal Levels

design for easy PCB layout.

• Supports Open, Short and Terminated Input

The DS90LV018A and companion LVDS line driver

Fail-Safe

provide a new alternative to high power PECL/ECL

• Conforms to ANSI/TIA/EIA-644 Standard

devices for high speed point-to-point interface

• Industrial Temperature Operating Range

applications.

– (−40°C to +85°C)

• Available in SOIC Package

Connection Diagram

Figure 1. SOIC

See Package Number D (R-PDSO-G8)

Functional Diagram

Truth Table

INPUTS OUTPUT

+] − [R

−] R

OUT

≥ 0.1V H

≤ −0.1V L

Full Fail-safe OPEN/SHORT or Terminated H

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (17 pages)

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DS90LV018A www.ti.com SNLS014D – JUNE 1998 – REVISED APRIL 2013 DS90LV018A 3V LVDS Single CMOS Differential Line Receiver Check for Samples: DS90LV018A FEATURES DESCRIPTION • • • • • • • • • The DS90LV018A is a single CMOS differential line receiver designed for applications requiring ultra low power dissipation, low noise and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology.
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DS90LV018A SNLS014D – JUNE 1998 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) −0.3V to +4V Supply Voltage (VCC) Input Voltage (RIN+, RIN−) −0.3V to +3.9V −0.3V to (VCC + 0.3V) Output Voltage (ROUT) Maximum Package Power Dissipation @ +25°C D Package 1025 mW Derate D Package 8.
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DS90LV018A www.ti.com SNLS014D – JUNE 1998 – REVISED APRIL 2013 Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (1) (2) Symbol Parameter Conditions VTH Differential Input High Threshold VTL Differential Input Low Threshold IIN Input Current VCM = +1.2V, 0V, 3V VIN = +2.8V (3) Pin Min RIN+, RIN− −100 VCC = 3.6V or 0V VIN = 0V VIN = +3.6V VOH VCC = 0V mV ±1 +10 μA −10 ±1 +10 μA +20 μA V 2.7 3.1 V IOH = −0.
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DS90LV018A SNLS014D – JUNE 1998 – REVISED APRIL 2013 www.ti.com PARAMETER MEASUREMENT INFORMATION Figure 2. Receiver Propagation Delay and Transition Time Test Circuit Figure 3. Receiver Propagation Delay and Transition Time Waveforms TYPICAL APPLICATION Balanced System Figure 4.
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DS90LV018A www.ti.com SNLS014D – JUNE 1998 – REVISED APRIL 2013 APPLICATION INFORMATION General application guidelines and hints for LVDS drivers and receivers may be found in the following application notes: LVDS Owner's Manual (lit #550062-001), AN-808 (SNLA028), AN-1035 (SNOA355), AN-977 (SNLA166), AN-971 (SNLA165), AN-916 (SNLA219), AN-805 (SNOA233), AN-903 (SNLA034). LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as is shown in Figure 4.
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DS90LV018A SNLS014D – JUNE 1998 – REVISED APRIL 2013 www.ti.com Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode rejection of the receivers. On the printed circuit board, this distance should remain constant to avoid discontinuities in differential impedance. Minor violations at connection points are allowable. TERMINATION Use a termination resistor which best matches the differential impedance or your transmission line.
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DS90LV018A www.ti.com SNLS014D – JUNE 1998 – REVISED APRIL 2013 Pin Descriptions Pin No. Name 1 RIN- Inverting receiver input pin Description 2 RIN+ Non-inverting receiver input pin 7 ROUT Receiver output pin 8 VCC Power supply pin, +3.3V ± 0.
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DS90LV018A SNLS014D – JUNE 1998 – REVISED APRIL 2013 www.ti.
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DS90LV018A www.ti.
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DS90LV018A SNLS014D – JUNE 1998 – REVISED APRIL 2013 www.ti.
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DS90LV018A www.ti.com SNLS014D – JUNE 1998 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision C (April 2013) to Revision D • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DS90LV018ATMX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 DS90LV018ATMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS90LV018ATMX SOIC D 8 2500 367.0 367.0 35.0 DS90LV018ATMX/NOPB SOIC D 8 2500 367.0 367.0 35.
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