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DS90LV031A

www.ti.com

SNLS020C –JULY 1999–REVISED APRIL 2013

DS90LV031A 3V LVDS Quad CMOS Differential Line Driver

Check for Samples: DS90LV031A

FEATURES

DESCRIPTION

The DS90LV031A is a quad CMOS differential line

• >400 Mbps (200 MHz) switching rates

driver designed for applications requiring ultra low

• 0.1 ns typical differential skew

power dissipation and high data rates. The device is

• 0.4 ns maximum differential skew

designed to support data rates in excess of 400 Mbps

(200 MHz) utilizing Low Voltage Differential Signaling

• 2.0 ns maximum propagation delay

(LVDS) technology.

• 3.3V power supply design

The DS90LV031A accepts low voltage

• ±350 mV differential signaling

LVTTL/LVCMOS input levels and translates them to

• Low power dissipation (13mW at 3.3V static)

low voltage (350 mV) differential output signals. In

• Interoperable with existing 5V LVDS devices

addition the driver supports a TRI-STATE

function

that may be used to disable the output stage,

• Compatible with IEEE 1596.3 SCI LVDS

disabling the load current, and thus dropping the

standard

device to an ultra low idle power state of 13 mW

• Compatible with TIA/EIA-644 LVDS standard

typical.

• Industrial operating temperature range

The EN and EN* inputs allow active Low or active

• Available in SOIC and TSSOP surface mount

High control of the TRI-STATE outputs. The enables

packaging

are common to all four drivers. The DS90LV031A and

companion line receiver (DS90LV032A) provide a

new alternative to high power psuedo-ECL devices

for high speed point-to-point interface applications.

Connection Diagram

Figure 1. Dual-In-Line

See Package Number D (R-PDSO-G16) or

PW (R-PDSO-G16)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2TRI-STATE is a registered trademark of Texas Instruments.

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (19 pages)

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DS90LV031A www.ti.com SNLS020C – JULY 1999 – REVISED APRIL 2013 DS90LV031A 3V LVDS Quad CMOS Differential Line Driver Check for Samples: DS90LV031A FEATURES DESCRIPTION • • • • • • • • • The DS90LV031A is a quad CMOS differential line driver designed for applications requiring ultra low power dissipation and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology.
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DS90LV031A SNLS020C – JULY 1999 – REVISED APRIL 2013 www.ti.com Functional Diagram Truth Table Enables Input Outputs EN EN* DIN DOUT+ DOUT− L H X Z Z L L H H H L All other combinations of ENABLE inputs These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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DS90LV031A www.ti.com SNLS020C – JULY 1999 – REVISED APRIL 2013 Absolute Maximum Ratings (1) −0.3V to +4V Supply Voltage (VCC) Input Voltage (DIN) −0.3V to (VCC + 0.3V) Enable Input Voltage (EN, EN*) −0.3V to (VCC + 0.3V) −0.3V to +3.9V Output Voltage (DOUT+, DOUT−) Short Circuit Duration (DOUT+, DOUT−) Continuous Maximum Package Power Dissipation @ +25°C D Package 1088 mW PW Package 866 mW Derate D Package 8.5 mW/°C above +25°C Derate PW Package 6.
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DS90LV031A SNLS020C – JULY 1999 – REVISED APRIL 2013 www.ti.com Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified.
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DS90LV031A www.ti.com SNLS020C – JULY 1999 – REVISED APRIL 2013 Switching Characteristics - Industrial VCC = +3.3V ±10%, TA = −40°C to +85°C Symbol (1) (2) (3) Parameter Conditions tPHLD Differential Propagation Delay High to Low tPLHD Differential Propagation Delay Low to High tSKD1 Differential Pulse Skew |tPHLD − tPLHD| tSKD2 Channel-to-Channel Skew RL = 100Ω, CL = 10 pF (Figure 3 and Figure 4) (4) (5) Min Typ Max Units 0.8 1.18 2.0 ns 0.8 1.25 2.0 ns 0 0.07 0.4 ns 0 0.
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DS90LV031A SNLS020C – JULY 1999 – REVISED APRIL 2013 www.ti.com Parameter Measurement Information Figure 2. Driver VOD and VOS Test Circuit Figure 3. Driver Propagation Delay and Transition Time Test Circuit Figure 4.
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DS90LV031A www.ti.com SNLS020C – JULY 1999 – REVISED APRIL 2013 Parameter Measurement Information (continued) Figure 5. Driver TRI-STATE Delay Test Circuit Figure 6.
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DS90LV031A SNLS020C – JULY 1999 – REVISED APRIL 2013 www.ti.com APPLICATION INFORMATION General application guidelines and hints for LVDS drivers and receivers may be found in the following application notes: LVDS Owner's Manual (SNLA187), AN-808 (SNLA028), AN-1035 (SNOA355), AN-977 (SNLA166), AN971 (SNLA165), AN-916 (SNLA219), AN-805 (SNOA233), AN-903 (SNLA034). LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as is shown in Figure 8.
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DS90LV031A www.ti.com SNLS020C – JULY 1999 – REVISED APRIL 2013 Differential Traces Use controlled impedance traces which match the differential impedance of your transmission medium (ie. cable) and termination resistor. Run the differential pair trace lines as close together as possible as soon as they leave the IC (stubs should be < 10mm long). This will help eliminate reflections and ensure noise is coupled as common-mode.
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DS90LV031A SNLS020C – JULY 1999 – REVISED APRIL 2013 www.ti.com Figure 7. Driver Output Levels TYPICAL APPLICATION Figure 8. Point-to-Point Application Typical Performance Curves Figure 9.
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DS90LV031A www.ti.com SNLS020C – JULY 1999 – REVISED APRIL 2013 Typical Performance Curves (continued) Figure 10. Typical DS90LV031A, DOUT vs RL, VCC = 3.3V, TA = 25°C PIN DESCRIPTIONS Pin No.
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DS90LV031A SNLS020C – JULY 1999 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision B (April 2013) to Revision C • 12 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device DS90LV031ATMTCX/NO PB Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TSSOP PW 16 2500 330.0 12.4 6.95 8.3 1.6 8.0 12.0 Q1 DS90LV031ATMX SOIC D 16 2500 330.0 16.4 6.5 10.3 2.3 8.0 16.0 Q1 DS90LV031ATMX/NOPB SOIC D 16 2500 330.0 16.4 6.5 10.3 2.3 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TSSOP PW 16 2500 367.0 367.0 35.0 DS90LV031ATMX SOIC D 16 2500 367.0 367.0 35.0 DS90LV031ATMX/NOPB SOIC D 16 2500 367.0 367.0 35.
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