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DS90LV047A

www.ti.com

SNLS044C –MAY 2000–REVISED APRIL 2013

DS90LV047A 3V LVDS Quad CMOS Differential Line Driver

Check for Samples: DS90LV047A

FEATURES

DESCRIPTION

The DS90LV047A is a quad CMOS flow-through

• >400 Mbps (200 MHz) Switching Rates

differential line driver designed for applications

• Flow-Through Pinout Simplifies PCB Layout

requiring ultra low power dissipation and high data

• 300 ps Typical Differential Skew

rates. The device is designed to support data rates in

excess of 400 Mbps (200 MHz) utilizing Low Voltage

• 400 ps Maximum Differential Skew

Differential Signaling (LVDS) technology.

• 1.7 ns Maximum Propagation Delay

The DS90LV047A accepts low voltage TTL/CMOS

• 3.3V Power Supply Design

input levels and translates them to low voltage (350

• ±350 mV Differential Signaling

mV) differential output signals. In addition, the driver

• Low Power Dissipation (13mW at 3.3V Static)

supports a TRI-STATE function that may be used to

disable the output stage, disabling the load current,

• Interoperable with Existing 5V LVDS Receivers

and thus dropping the device to an ultra low idle

• High impedance on LVDS Outputs on Power

power state of 13 mW typical. The DS90LV047A has

Down

a flow-through pinout for easy PCB layout.

• Conforms to TIA/EIA-644 LVDS Standard

The EN and EN* inputs are ANDed together and

• Industrial Operating Temperature Range

control the TRI-STATE outputs. The enables are

(−40°C to +85°C)

common to all four drivers. The DS90LV047A and

companion line receiver (DS90LV048A) provide a

• Available in Surface Mount (SOIC) and Low

new alternative to high power psuedo-ECL devices

Profile TSSOP Package

for high speed point-to-point interface applications.

Connection Diagram

Figure 1. Order Number DS90LV047ATM, DS90LV047ATMTC

D0016A, PW0016A Packages

Truth Table

ENABLES INPUT OUTPUTS

EN EN* D

OUT+

OUT−

H L or Open L L H

H H L

All other combinations of ENABLE inputs X Z Z

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (21 pages)

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DS90LV047A www.ti.com SNLS044C – MAY 2000 – REVISED APRIL 2013 DS90LV047A 3V LVDS Quad CMOS Differential Line Driver Check for Samples: DS90LV047A FEATURES DESCRIPTION • • • • • • • • • • The DS90LV047A is a quad CMOS flow-through differential line driver designed for applications requiring ultra low power dissipation and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology.
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DS90LV047A SNLS044C – MAY 2000 – REVISED APRIL 2013 www.ti.com Functional Diagram These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) −0.3V to +4V Supply Voltage (VCC) Input Voltage (DIN) −0.3V to (VCC + 0.3V) Enable Input Voltage (EN, EN*) −0.3V to (VCC + 0.3V) −0.3V to +3.
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DS90LV047A www.ti.
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DS90LV047A SNLS044C – MAY 2000 – REVISED APRIL 2013 www.ti.com Switching Characteristics VCC = +3.3V ± 10%, TA = −40°C to +85°C (1) (2) (3) Symbol Parameter Conditions RL = 100Ω, CL = 15 pF (Figure 3 and Figure 4) Min Typ Max Units 0.5 0.9 1.7 ns 0.5 1.2 1.7 ns tPHLD Differential Propagation Delay High to Low tPLHD Differential Propagation Delay Low to High tSKD1 Differential Pulse Skew |tPHLD − tPLHD| (4) 0 0.3 0.4 ns tSKD2 Channel-to-Channel Skew (5) 0 0.4 0.
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DS90LV047A www.ti.com SNLS044C – MAY 2000 – REVISED APRIL 2013 Parameter Measurement Information (continued) Figure 4. Driver Propagation Delay and Transition Time Waveforms Figure 5. Driver TRI-STATE Delay Test Circuit Figure 6.
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DS90LV047A SNLS044C – MAY 2000 – REVISED APRIL 2013 www.ti.com Typical Application Figure 7. Point-to-Point Application APPLICATION INFORMATION General application guidelines and hints for LVDS drivers and receivers may be found in the following application notes: LVDS Owner's Manual (lit #550062-001), AN808, AN977, AN971, AN916, AN805, AN903. LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as is shown in Figure 7.
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DS90LV047A www.ti.com SNLS044C – MAY 2000 – REVISED APRIL 2013 POWER DECOUPLING RECOMMENDATIONS Bypass capacitors must be used on power pins. Use high frequency ceramic (surface mount is recommended) 0.1μF and 0.001μF capacitors in parallel at the power supply pin with the smallest value capacitor closest to the device supply pin. Additional scattered capacitors over the printed circuit board will improve decoupling. Multiple vias should be used to connect the decoupling capacitors to the power planes.
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DS90LV047A SNLS044C – MAY 2000 – REVISED APRIL 2013 www.ti.com Balanced cables (e.g. twisted pair) are usually better than unbalanced cables (ribbon cable, simple coax.) for noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and also tend to pick up electromagnetic radiation a common-mode (not differential mode) noise which is rejected by the receiver. For cable distances < 0.5M, most cables can be made to work effectively. For distances 0.
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DS90LV047A www.ti.com SNLS044C – MAY 2000 – REVISED APRIL 2013 PIN DESCRIPTIONS Pin No. Name Description 2, 3, 6, 7 DIN 10, 11, 14, 15 DOUT+ Driver input pin, TTL/CMOS compatible Non-inverting driver output pin, LVDS levels 9, 12, 13, 16 DOUT− Inverting driver output pin, LVDS levels 1 EN Driver enable pin: When EN is low, the driver is disabled. When EN is high and EN* is low or open, the driver is enabled. If both EN and EN* are open circuit, then the driver is disabled.
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DS90LV047A SNLS044C – MAY 2000 – REVISED APRIL 2013 www.ti.com Typical Performance Curves 10 Figure 9. Output High Voltage vs Power Supply Voltage Figure 10. Output Low Voltage vs Power Supply Voltage Figure 11. Output Short Circuit Current vs Power Supply Voltage Figure 12. Output TRI-STATE Current vs Power Supply Voltage Figure 13. Differential Output Voltage vs Power Supply Voltage Figure 14.
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DS90LV047A www.ti.com SNLS044C – MAY 2000 – REVISED APRIL 2013 Typical Performance Curves (continued) Figure 15. Offset Voltage vs Power Suppy Voltage Figure 16. Power Supply Current vs Frequency Figure 17. Power Supply Current vs Power Supply Voltage Figure 18. Power Supply Current vs Ambient Temperature Figure 19. Differential Propagation Delay vs Power Supply Voltage Figure 20.
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DS90LV047A SNLS044C – MAY 2000 – REVISED APRIL 2013 www.ti.com Typical Performance Curves (continued) Figure 21. Differential Skew vs Power Supply Voltage Figure 22. Differential Skew vs Ambient Temperature Figure 23. Transition Time vs Power Supply Voltage Figure 24. Transition Time vs Ambient Temperature Figure 25.
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DS90LV047A www.ti.com SNLS044C – MAY 2000 – REVISED APRIL 2013 Data Rate vs Cable Length Graph Test Procedure A pseudo-random bit sequence (PRBS) of 29−1 bits was programmed into a function generator (Tektronix HFS9009) and connected to the driver inputs via 50Ω cables and SMB connectors. An oscilloscope (Tektronix 11801B) was used to probe the resulting eye pattern, measured differentially at the input to the receiver. A 100Ω resistor was used to terminate the pair at the far end of the cable.
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DS90LV047A SNLS044C – MAY 2000 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision B (April 2013) to Revision C • 14 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DS90LV047ATMTCX TSSOP PW 16 2500 330.0 12.4 6.95 8.3 1.6 8.0 12.0 Q1 DS90LV047ATMX/NOPB SOIC D 16 2500 330.0 16.4 6.5 10.3 2.3 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS90LV047ATMTCX TSSOP PW 16 2500 367.0 367.0 35.0 DS90LV047ATMX/NOPB SOIC D 16 2500 367.0 367.0 35.
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