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DS90LV048A

www.ti.com

SNLS045B –JULY 1999–REVISED APRIL 2013

DS90LV048A 3V LVDS Quad CMOS Differential Line Receiver

Check for Samples: DS90LV048A

FEATURES

DESCRIPTION

The DS90LV048A is a quad CMOS flow-through

• >400 Mbps (200 MHz) Switching Rates

differential line receiver designed for applications

• Flow-Through Pinout Simplifies PCB Layout

requiring ultra low power dissipation and high data

• 150 ps Channel-to-Channel Skew (Typical)

rates. The device is designed to support data rates in

excess of 400 Mbps (200 MHz) utilizing Low Voltage

• 100 ps Differential Skew (Typical)

Differential Signaling (LVDS) technology.

• 2.7 ns Maximum Propagation Delay

The DS90LV048A accepts low voltage (350 mV

• 3.3V Power Supply Design

typical) differential input signals and translates them

• High Impedance LVDS Inputs on Power Down

to 3V CMOS output levels. The receiver supports a

• Low Power Design (40mW @ 3.3V Static)

TRI-STATE function that may be used to multiplex

outputs. The receiver also supports open, shorted

• Interoperable with Existing 5V LVDS Drivers

and terminated (100Ω) input fail-safe. The receiver

• Accepts Small Swing (350 mV Typical)

output will be HIGH for all fail-safe conditions. The

Differential Signal Levels

DS90LV048A has a flow-through pinout for easy PCB

• Supports Open, Short and Terminated Input

layout.

Fail-Safe

The EN and EN* inputs are ANDed together and

• 0V to −100mV Threshold Region

control the TRI-STATE outputs. The enables are

common to all four receivers. The DS90LV048A and

• Conforms to ANSI/TIA/EIA-644 Standard

companion LVDS line driver (eg. DS90LV047A)

• Industrial Temperature Operating Range (-40°C

provide a new alternative to high power PECL/ECL

to +85°C)

devices for high speed point-to-point interface

• Available in SOIC and TSSOP Package

applications.

Connection Diagram

Order Number DS90LV048ATM, DS90LV048ATMTC

D0016A, PW0016A Packages

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (20 pages)

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DS90LV048A www.ti.com SNLS045B – JULY 1999 – REVISED APRIL 2013 DS90LV048A 3V LVDS Quad CMOS Differential Line Receiver Check for Samples: DS90LV048A FEATURES DESCRIPTION • • • • • • • • • • The DS90LV048A is a quad CMOS flow-through differential line receiver designed for applications requiring ultra low power dissipation and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology.
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DS90LV048A SNLS045B – JULY 1999 – REVISED APRIL 2013 www.ti.com Functional Diagram TRUTH TABLE ENABLES EN EN* H L or Open All other combinations of ENABLE inputs INPUTS OUTPUT RIN+ − RIN− ROUT VID ≥ 0V H VID ≤ −0.1V L Full Fail-safe OPEN/SHORT or Terminated H X Z These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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DS90LV048A www.ti.com SNLS045B – JULY 1999 – REVISED APRIL 2013 ABSOLUTE MAXIMUM RATINGS (1) (2) Supply Voltage (VCC) −0.3V to +4V Input Voltage (RIN+, RIN−) −0.3V to 3.9V Enable Input Voltage (EN, EN*) −0.3V to (VCC + 0.3V) Output Voltage (ROUT) −0.3V to (VCC + 0.3V) Maximum Package Power Dissipation @ +25°C D0016A Package 1025 mW PW0016A Package 866 mW Derate D0016A Package 8.2 mW/°C above +25°C Derate PW0016A Package 6.
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DS90LV048A SNLS045B – JULY 1999 – REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (1) (2) Symbol Parameter Conditions VCM = +1.2V, 0.05V, 2.95V (3) Pin Min RIN+, RIN− −100 VTH Differential Input High Threshold VTL Differential Input Low Threshold VCMR Common-Mode Voltage Range VID = 200mV pk to pk (4) 0.1 IIN Input Current VIN = +2.
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DS90LV048A www.ti.com SNLS045B – JULY 1999 – REVISED APRIL 2013 SWITCHING CHARACTERISTICS Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (1) (2) (3) (4) Symbol Parameter Conditions Min Typ Max Units 1.2 2.0 2.7 ns 1.2 1.9 2.7 ns 0 0.1 0.4 ns 0 0.15 0.5 ns tSKD3 Differential Part to Part Skew (4) 1.0 ns tSKD4 Differential Part to Part Skew (6) 1.5 ns tTLH Rise Time 0.5 1.0 ns tTHL Fall Time 0.35 1.
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DS90LV048A SNLS045B – JULY 1999 – REVISED APRIL 2013 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) CL includes load and test jig capacitance. S1 = VCC for tPZL and tPLZ measurements. S1 = GND for tPZH and tPHZ measurements. Figure 3. Receiver TRI-STATE Delay Test Circuit Figure 4. Receiver TRI-STATE Delay Waveforms TYPICAL APPLICATION Balanced System Figure 5.
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DS90LV048A www.ti.com SNLS045B – JULY 1999 – REVISED APRIL 2013 APPLICATION INFORMATION General application guidelines and hints for LVDS drivers and receivers may be found in the following application notes: LVDS Owner's Manual (lit #550062-002), AN-808 (SNLA028), AN-977 (SNLA166), AN-971 (SNLA165), AN-916 (SNLA219), AN-805 (SNOA233), AN-903 (SNLA034). The latest applications material is available on the web at: www.ti.
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DS90LV048A SNLS045B – JULY 1999 – REVISED APRIL 2013 www.ti.com Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase difference between signals which destroys the magnetic field cancellation benefits of differential signals and EMI will result. (Note the velocity of propagation, v = c/Er where c (the speed of light) = 0.2997mm/ps or 0.0118 in/ps). Do not rely solely on the autoroute function for differential traces.
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DS90LV048A www.ti.com SNLS045B – JULY 1999 – REVISED APRIL 2013 Figure 6. VTC of the DS90LV048A LVDS Receiver Fail-Safe Feature The LVDS receiver is a high gain, high speed device that amplifies a small differential signal (20mV) to CMOS logic levels. Due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from appearing as a valid signal.
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DS90LV048A SNLS045B – JULY 1999 – REVISED APRIL 2013 www.ti.
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DS90LV048A www.ti.
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DS90LV048A SNLS045B – JULY 1999 – REVISED APRIL 2013 www.ti.
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DS90LV048A www.ti.com SNLS045B – JULY 1999 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision A (April 2013) to Revision B • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DS90LV048ATMTCX TSSOP PW 16 2500 330.0 12.4 6.95 8.3 1.6 8.0 12.0 Q1 DS90LV048ATMX/NOPB SOIC D 16 2500 330.0 16.4 6.5 10.3 2.3 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS90LV048ATMTCX TSSOP PW 16 2500 367.0 367.0 35.0 DS90LV048ATMX/NOPB SOIC D 16 2500 367.0 367.0 35.
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