Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - serialisers FPD-Link III, LVDS LLP 40 EP

DS90UB903Q, DS90UB904Q

www.ti.com

SNLS332E –JUNE 2010–REVISED APRIL 2013

DS90UB903Q/DS90UB904Q 10 - 43MHz 18 Bit Color FPD-Link III Serializer and

Deserializer with Bidirectional Control Channel

Check for Samples: DS90UB903Q, DS90UB904Q

FEATURES

DESCRIPTION

The DS90UB903Q/DS90UB904Q chipset offers a

• 10 MHz to 43 MHz Input PCLK Support

FPD-Link III interface with a high-speed forward

• 210 Mbps to 903 Mbps Data Throughput

channel and a bidirectional control channel for data

• Single Differential Pair Interconnect

transmission over a single differential pair. The

DS90UB903Q/904Q incorporates differential

• Bidirectional Control Interface Channel with

signaling on both the high-speed forward channel and

C Support

bidirectional control channel data paths. The

• Embedded Clock with DC Balanced Coding to

Serializer/ Deserializer pair is targeted for direct

Support AC-Coupled Interconnects

connections between graphics host controller and

• Capable to Drive up to 10 Meters Shielded

displays modules. This chipset is ideally suited for

driving video data to displays requiring 18-bit color

Twisted-Pair

depth (RGB666 + HS, VS, and DE) along with

• I

C Compatible Serial Interface

bidirectional control channel bus. The primary

• Single Hardware Device Addressing Pin

transport converts 21 bit data over a single high-

• Up to 4 General Purpose Input (GPI)/ Output speed serial stream, along with a separate low

latency bidirectional control channel transport that

(GPO)

accepts control information from an I

C port. Using

• LOCK Output Reporting Pin and AT-SPEED

TI’s embedded clock technology allows transparent

BIST Diagnosis Feature to Validate Link

full-duplex communication over a single differential

Integrity

pair, carrying asymmetrical bidirectional control

• Integrated Termination Resistors

channel information in both directions. This single

serial stream simplifies transferring a wide data bus

• 1.8V- or 3.3V-Compatible Parallel Bus Interface

over PCB traces and cable by eliminating the skew

• Single Power Supply at 1.8V

problems between parallel data and clock paths. This

• ISO 10605 ESD and IEC 61000-4-2 ESD

significantly saves system cost by narrowing data

Compliant

paths that in turn reduce PCB layers, cable width,

and connector size and pins.

• Automotive Grade Product: AEC-Q100 Grade 2

Qualified

In addition, the Deserializer inputs provide

equalization control to compensate for loss from the

• Temperature Range −40°C to +105°C

media over longer distances. Internal DC balanced

• No Reference Clock Required on Deserializer

encoding/decoding is used to support AC-Coupled

• Programmable Receive Equalization

interconnects.

• EMI/EMC Mitigation

The Serializer is offered in a 40-pin lead in WQFN

– DES Programmable Spread Spectrum

and Deserializer is offered in a 48-pin WQFN

(SSCG) Outputs

packages.

– DES Receiver Staggered Outputs

APPLICATIONS

• Automotive Display Systems

– Central Information Displays

– Navigation Displays

– Rear Seat Entertainment

– Touch Screen Displays

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (45 pages)

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DS90UB903Q, DS90UB904Q www.ti.com SNLS332E – JUNE 2010 – REVISED APRIL 2013 DS90UB903Q/DS90UB904Q 10 - 43MHz 18 Bit Color FPD-Link III Serializer and Deserializer with Bidirectional Control Channel Check for Samples: DS90UB903Q, DS90UB904Q FEATURES DESCRIPTION • • • • The DS90UB903Q/DS90UB904Q chipset offers a FPD-Link III interface with a high-speed forward channel and a bidirectional control channel for data transmission over a single differential pair.
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DS90UB903Q, DS90UB904Q SNLS332E – JUNE 2010 – REVISED APRIL 2013 www.ti.com Typical Application Diagram FPD-Link III Parallel Data In 18+3 Graphics Controller -Video Processor Parallel Data Out 18+3 4 Display Module, Touch Panel 4 DS90UB903Q DS90UB904Q GPO GPI Bidirectional Control Channel 2 Bidirectional Control Bus 2 Bidirectional Control Bus Deserializer Serializer Figure 1.
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DS90UB903Q, DS90UB904Q www.ti.
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DS90UB903Q, DS90UB904Q SNLS332E – JUNE 2010 – REVISED APRIL 2013 www.ti.com DS90UB903Q SERIALIZER PIN DESCRIPTIONS (continued) Pin Name Pin No. PDB 13 RES 10, 11 I/O, Type Description Power down Mode Input Pin. PDB = H, Serializer is enabled and is ON. Input, LVCMOS PDB = L, Serailizer is in Power Down mode. When the Serializer is in Power Down, w/ pull down the PLL is shutdown, and IDD is minimized.
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DS90UB903Q, DS90UB904Q www.ti.
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DS90UB903Q, DS90UB904Q SNLS332E – JUNE 2010 – REVISED APRIL 2013 www.ti.com DS90UB904Q DESERIALIZER PIN DESCRIPTIONS (continued) Pin Name Pin No. PDB 35 LOCK 34 RES I/O, Type Description Power down Mode Input Pin. PDB = H, Deserializer is enabled and is ON. Input, LVCMOS PDB = L, Deserializer is in Power Down mode. When the Deserializer is in Power w/ pull down Down. Programmed control register data are NOT retained and reset to default values.
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DS90UB903Q, DS90UB904Q www.ti.com SNLS332E – JUNE 2010 – REVISED APRIL 2013 Absolute Maximum Ratings (1) (2) (3) −0.3V to +2.5V Supply Voltage – VDDn (1.8V) −0.3V to +4.0V Supply Voltage – VDDIO −0.3V to + (VDDIO + 0.3V) LVCMOS Input Voltage I/O Voltage −0.3V to +(VDD + 0.3V) CML Driver I/O Voltage (VDD) −0.3V to (VDD + 0.
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DS90UB903Q, DS90UB904Q SNLS332E – JUNE 2010 – REVISED APRIL 2013 www.ti.com Electrical Characteristics (1) (2) (3) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units LVCMOS DC SPECIFICATIONS 3.3V I/O (SER INPUTS, DES OUTPUTS, GPI, GPO, CONTROL INPUTS AND OUTPUTS) VIH High Level Input Voltage VIN = 3.0V to 3.6V 2.0 VIN V VIL Low Level Input Voltage VIN = 3.0V to 3.6V GND 0.
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DS90UB903Q, DS90UB904Q www.ti.com SNLS332E – JUNE 2010 – REVISED APRIL 2013 Electrical Characteristics(1)(2)(3) (continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Differential Threshold High Voltage VTH Conditions Min Typ Max Units +90 (Figure 10) mV VTL Differential Threshold Low Voltage VIN Differential Input Voltage Range RIN+ - RIN- 180 IIN Input Current VIN = VDD or 0V, VDD = 1.
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DS90UB903Q, DS90UB904Q SNLS332E – JUNE 2010 – REVISED APRIL 2013 www.ti.com Serializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified.
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DS90UB903Q, DS90UB904Q www.ti.com SNLS332E – JUNE 2010 – REVISED APRIL 2013 Deserializer Switching Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Pin/Freq. Min Typ Max Units 4.571T +8 4.571T + 12 4.
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DS90UB903Q, DS90UB904Q SNLS332E – JUNE 2010 – REVISED APRIL 2013 www.ti.com Bidirectional Control Bus AC Timing Specifications (SCL, SDA) - I2C Compliant Over recommended supply and temperature ranges unless otherwise specified. See Figure 4. Symbol Parameter Conditions RECOMMENDED INPUT TIMING REQUIREMENTS Min Typ Max Units 100 kHz (1) fSCL SCL Clock Frequency >0 tLOW SCL Low Period 4.7 µs tHIGH SCL High Period 4.0 µs tHD:STA Hold time for a start or a repeated start condition 4.
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DS90UB903Q, DS90UB904Q www.ti.com SNLS332E – JUNE 2010 – REVISED APRIL 2013 SDA tf tHD;STA tLOW tBUF tr tf tr SCL tSU;STA tHD;STA tHIGH tSU;STO tSU;DAT tHD;DAT START STOP REPEATED START START Figure 4. Bidirectional Control Bus Timing Bidirectional Control Bus DC Characteristics (SCL, SDA) - I2C Compliant Over recommended supply and temperature ranges unless otherwise specified. Symbol Parameter Max Units SDA and SCL 0.
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DS90UB903Q, DS90UB904Q SNLS332E – JUNE 2010 – REVISED APRIL 2013 www.ti.com 100 nF DOUT+ 50: ZDiff = 100: SCOPE BW 8 4.0 GHz 100: 50: DOUT- 100 nF 21 DIN PARALLEL-TO-SERIAL Figure 7. Serializer CML Output Load and Transition Times DOUT+ RL DOUT- PCLK Figure 8. Serializer VOD DC Diagram DOUT- Single Ended V V OD V OD+ ODV DOUT+ | OS 0V Differential V OD+ 0V (DOUT+)-(DOUT-) V OD- Figure 9.
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DS90UB903Q, DS90UB904Q www.ti.com SNLS332E – JUNE 2010 – REVISED APRIL 2013 tTCP PCLK VDDIO/2 tDIS VDDIO/2 VDDIO/2 tDIH VDDIO DINn VDDIO/2 Setup Hold VDDIO/2 0V Figure 12. Serializer Setup/Hold Times PDB VDDIO/2 PCLK tPLD TRI-STATE DOUT± TRI-STATE Output Active SYMBOL N+2 | | SYMBOL N+1 | | SYMBOL N | | DIN | | Figure 13.
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DS90UB903Q, DS90UB904Q SYMBOL N + 3 SYMBOL N + 3 | | SYMBOL N + 2 | | 0V | | SYMBOL N + 1 | | SYMBOL N RIN± www.ti.com | | SNLS332E – JUNE 2010 – REVISED APRIL 2013 tDD PCLK SYMBOL N - 1 | || SYMBOL N - 2 | || SYMBOL N - 3 | || | || | || ROUTn VDDIO/2 SYMBOL N SYMBOL N+1 Figure 17. Deserializer Delay tRCP PCLK VDDIO 1/2 VDDIO 1/2 VDDIO 0V VDDIO ROUT[n], VS, HS 1/2 VDDIO 1/2 VDDIO 0V tROS tROH Figure 18.
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DS90UB903Q, DS90UB904Q www.ti.com SNLS332E – JUNE 2010 – REVISED APRIL 2013 0.62 JITTER AMPLITUDE (UI) 0.61 0.60 0.59 0.58 0.57 0.56 0.55 0.54 0.53 0.52 1.0E+04 1.0E+05 1.0E+06 1.0E+07 JITTER FREQUENCY (Hz) Figure 21. Typical Deserializer Input Jitter Tolerance Curve at 43 MHz Frequency FPCLK+ fdev fdev (max) FPCLK FPCLK- fdev (min) Time 1 / fmod Figure 22.
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DS90UB903Q, DS90UB904Q SNLS332E – JUNE 2010 – REVISED APRIL 2013 www.ti.com Table 1. DS90UB903Q Control Registers Addr (Hex) 0 Name R/W 7:1 DEVICE ID 0 SER ID SEL 7:3 RESERVED RW Default 0xB0'h 0x00'h Description 7-bit address of Serializer; 0x58'h (1011_000X'b) default 0: Device ID is from ID[x] 1: Register I2C Device ID overrides ID[x] Reserved Standby mode control. Retains control register data. Supported only when MODE = 0 0: Enabled. Low-current Standby mode with wake-up capability.
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DS90UB903Q, DS90UB904Q www.ti.com SNLS332E – JUNE 2010 – REVISED APRIL 2013 Table 1.
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DS90UB903Q, DS90UB904Q SNLS332E – JUNE 2010 – REVISED APRIL 2013 www.ti.com Table 2.
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DS90UB903Q, DS90UB904Q www.ti.com SNLS332E – JUNE 2010 – REVISED APRIL 2013 Table 2.
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DS90UB903Q, DS90UB904Q SNLS332E – JUNE 2010 – REVISED APRIL 2013 www.ti.com Table 2.
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DS90UB903Q, DS90UB904Q www.ti.com SNLS332E – JUNE 2010 – REVISED APRIL 2013 FUNCTIONAL DESCRIPTION The DS90UB903Q/904Q FPD-Link III chipset is intended for video display applications. The Serializer/ Deserializer chipset operates from a 10 MHz to 43 MHz pixel clock frequency. The DS90UB903Q transforms a 21-bit wide parallel LVCMOS data bus along with a bidirectional control bus into a single high-speed differential pair.
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DS90UB903Q, DS90UB904Q SNLS332E – JUNE 2010 – REVISED APRIL 2013 www.ti.com DESCRIPTION OF BIDIRECTIONAL CONTROL BUS AND I2C MODES The I2C compatible interface allows programming of the DS90UB903Q, DS90UB904Q, or an external remote device (such as a display) through the bidirectional control channel. Register programming transactions to/from the DS90UB903Q/904Q chipset are employed through the clock (SCL) and data (SDA) lines.
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DS90UB903Q, DS90UB904Q www.ti.com SNLS332E – JUNE 2010 – REVISED APRIL 2013 SDA SCL S START condition, or START repeat condition P STOP condition Figure 28.
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DS90UB903Q, DS90UB904Q SNLS332E – JUNE 2010 – REVISED APRIL 2013 www.ti.com SLAVE CLOCK STRETCHING In order to communicate and synchronize with remote devices on the I2C bus through the bidirectional control channel, slave clock stretching must be supported by the I2C master controller/MCU. The chipset utilizes bus clock stretching (holding the SCL line low) during data transmission; where the I2C slave pulls the SCL line low prior to the 9th clock of every I2C data transfer (before the ACK signal).
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DS90UB903Q, DS90UB904Q www.ti.com SNLS332E – JUNE 2010 – REVISED APRIL 2013 Table 4. ID[x] Resistor Value – DS90UB904Q ID[x] Resistor Value - DS90UB904Q Des (1) Resistor RID Ω (±0.1%) Address 7'b (1) Address 8'b 0 appended (WRITE) 0, GND 7b' 110 0000 (h'60) 8b' 1100 0000 (h'C0) 2.0k 7b' 110 0001 (h'61) 8b' 1100 0010 (h'C2) 4.7k 7b' 110 0010 (h'62) 8b' 1100 0100 (h'C4) 8.2k 7b' 110 0011 (h'63) 8b' 1101 0110 (h'C6) 12.1k 7b' 110 0100 (h'64) 8b' 1101 1000 (h'C8) 39.
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DS90UB903Q, DS90UB904Q SNLS332E – JUNE 2010 – REVISED APRIL 2013 www.ti.com To configure the devices for display mode operation, set the Serializer MODE pin to High and the Deserializer MODE pin to Low. Before initiating any I2C commands, the Serializer needs to be programmed with the target slave device address and Serializer device address. DES_DEV_ID Register 0x06h sets the Deserializer device address and SLAVE_DEV_ID register 0x7h sets the remote target slave address.
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DS90UB903Q, DS90UB904Q www.ti.com SNLS332E – JUNE 2010 – REVISED APRIL 2013 AT-SPEED BIST (BISTEN, PASS) An optional AT SPEED Built in Self Test (BIST) feature supports at speed testing of the high-speed serial and the bidirectional control channel link. Control pins at the Deserializer are used to enable the BIST test mode and allow the system to initiate the test and set the duration. A HIGH on PASS pin indicates that all payloads received during the test were error free during the BIST duration test.
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DS90UB903Q, DS90UB904Q SNLS332E – JUNE 2010 – REVISED APRIL 2013 www.ti.com The Deserializer GPI[1:0] set to 00 will bypass the on-chip oscillator and an external oscillator to Serializer PCLK input is required. This allows the user to operate BIST under different frequencies other than the predefined ranges. Step 2: Enable AT SPEED BIST by placing the Serializer into BIST mode. Deserializer will communicate through the bidirectional control channel to configure Serializer into BIST mode.
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DS90UB903Q, DS90UB904Q www.ti.com SNLS332E – JUNE 2010 – REVISED APRIL 2013 fpixel (MHz) BIST Duration (s) x Total Pixels Transmitted = Total Bits Transmitted = BIST Duration (s) x Pixel 1 Pixel period (ns) x Total Bits Bit (Pixel) Error Rate -1 = [Total Bits Transmitted] (for passing BIST) = [Total Bits Transmitted x Bits/Pixel] -1 Figure 34. BIST BER Calculation Step 4: Place system in Normal Operating Mode by disabling BIST at the Serializer.
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DS90UB903Q, DS90UB904Q SNLS332E – JUNE 2010 – REVISED APRIL 2013 www.ti.com POWER UP REQUIREMENTS AND PDB PIN It is required to delay and release the PDB input signal after VDD (VDDn and VDDIO) power supplies have settled to the recommended operating voltages. A external RC network can be connected to the PDB pin to ensure PDB arrives after all the VDD have stabilized.
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DS90UB903Q, DS90UB904Q www.ti.com SNLS332E – JUNE 2010 – REVISED APRIL 2013 APPLICATIONS INFORMATION AC COUPLING The SER/DES supports only AC-coupled interconnects through an integrated DC balanced decoding scheme. External AC coupling capacitors must be placed in series in the FPD-Link III signal path as illustrated in Figure 36. DOUT+ RIN+ DOUT- RIN- D R Figure 36.
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DS90UB903Q, DS90UB904Q SNLS332E – JUNE 2010 – REVISED APRIL 2013 www.ti.com Figure 38 shows a typical connection of the DS90UB904Q Deserializer. DS90UB904Q (DES) 1.
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DS90UB903Q, DS90UB904Q www.ti.com SNLS332E – JUNE 2010 – REVISED APRIL 2013 rate increases as the cable length decreases. Therefore, the chipset supports 50 MHz at shorter distances. Other cable parameters that may limit the cable's performance boundaries are: cable attenuation, near-end crosstalk and pair-to-pair skew. The maximum length of cable that can be used is dependant on the quality of the cable (gauge, impedance), connector, board (discontinuities, power plane), the electrical environment (e.g.
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DS90UB903Q, DS90UB904Q SNLS332E – JUNE 2010 – REVISED APRIL 2013 www.ti.com Some devices provide separate power for different portions of the circuit. This is done to isolate switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power pin pairs.
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DS90UB903Q, DS90UB904Q www.ti.com SNLS332E – JUNE 2010 – REVISED APRIL 2013 Revision History 04/16/2012 • Added CMLOUT P/N in DS90UB904Q Deserializer Pin Descriptions • Added ESD CDM and ESD MM values • Added 3.3V I/O VOH conditions: IOH = -4 mA • Corrected 3.
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DS90UB903Q, DS90UB904Q SNLS332E – JUNE 2010 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision D (April 2013) to Revision E • 38 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 16-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing DS90UB903QSQ/NOPB WQFN RTA 40 DS90UB903QSQE/NOPB WQFN RTA DS90UB903QSQX/NOPB WQFN RTA DS90UB904QSQ/NOPB WQFN DS90UB904QSQE/NOPB DS90UB904QSQX/NOPB SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q1 40 250 178.0 16.4 6.3 6.3 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS90UB903QSQ/NOPB WQFN RTA 40 1000 367.0 367.0 38.0 DS90UB903QSQE/NOPB WQFN RTA 40 250 213.0 191.0 55.0 DS90UB903QSQX/NOPB WQFN RTA 40 2500 367.0 367.0 38.0 DS90UB904QSQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 DS90UB904QSQE/NOPB WQFN RHS 48 250 213.0 191.0 55.
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MECHANICAL DATA RTA0040A SQA40A (Rev B) www.ti.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.