Datasheet
DS90UB903Q, DS90UB904Q
www.ti.com
SNLS332E –JUNE 2010–REVISED APRIL 2013
DS90UB903Q/DS90UB904Q 10 - 43MHz 18 Bit Color FPD-Link III Serializer and
Deserializer with Bidirectional Control Channel
Check for Samples: DS90UB903Q, DS90UB904Q
1
FEATURES
DESCRIPTION
The DS90UB903Q/DS90UB904Q chipset offers a
2
• 10 MHz to 43 MHz Input PCLK Support
FPD-Link III interface with a high-speed forward
• 210 Mbps to 903 Mbps Data Throughput
channel and a bidirectional control channel for data
• Single Differential Pair Interconnect
transmission over a single differential pair. The
DS90UB903Q/904Q incorporates differential
• Bidirectional Control Interface Channel with
signaling on both the high-speed forward channel and
I
2
C Support
bidirectional control channel data paths. The
• Embedded Clock with DC Balanced Coding to
Serializer/ Deserializer pair is targeted for direct
Support AC-Coupled Interconnects
connections between graphics host controller and
• Capable to Drive up to 10 Meters Shielded
displays modules. This chipset is ideally suited for
driving video data to displays requiring 18-bit color
Twisted-Pair
depth (RGB666 + HS, VS, and DE) along with
• I
2
C Compatible Serial Interface
bidirectional control channel bus. The primary
• Single Hardware Device Addressing Pin
transport converts 21 bit data over a single high-
• Up to 4 General Purpose Input (GPI)/ Output speed serial stream, along with a separate low
latency bidirectional control channel transport that
(GPO)
accepts control information from an I
2
C port. Using
• LOCK Output Reporting Pin and AT-SPEED
TI’s embedded clock technology allows transparent
BIST Diagnosis Feature to Validate Link
full-duplex communication over a single differential
Integrity
pair, carrying asymmetrical bidirectional control
• Integrated Termination Resistors
channel information in both directions. This single
serial stream simplifies transferring a wide data bus
• 1.8V- or 3.3V-Compatible Parallel Bus Interface
over PCB traces and cable by eliminating the skew
• Single Power Supply at 1.8V
problems between parallel data and clock paths. This
• ISO 10605 ESD and IEC 61000-4-2 ESD
significantly saves system cost by narrowing data
Compliant
paths that in turn reduce PCB layers, cable width,
and connector size and pins.
• Automotive Grade Product: AEC-Q100 Grade 2
Qualified
In addition, the Deserializer inputs provide
equalization control to compensate for loss from the
• Temperature Range −40°C to +105°C
media over longer distances. Internal DC balanced
• No Reference Clock Required on Deserializer
encoding/decoding is used to support AC-Coupled
• Programmable Receive Equalization
interconnects.
• EMI/EMC Mitigation
The Serializer is offered in a 40-pin lead in WQFN
– DES Programmable Spread Spectrum
and Deserializer is offered in a 48-pin WQFN
(SSCG) Outputs
packages.
– DES Receiver Staggered Outputs
APPLICATIONS
• Automotive Display Systems
– Central Information Displays
– Navigation Displays
– Rear Seat Entertainment
– Touch Screen Displays
1
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Products conform to specifications per the terms of the Texas
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