Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - deserialisers LVCMOS WQFN 48

DS90UB913Q, DS90UB914Q

www.ti.com

SNLS420B –JULY 2012–REVISED APRIL 2013

DS90UB913Q/DS90UB914Q 10-100MHz 10/12- Bit DC-Balanced FPD-Link III Serializer and

Deserializer with Bidirectional Control Channel

Check for Samples: DS90UB913Q, DS90UB914Q

FEATURES

DESCRIPTION

The DS90UB913Q/DS90UB914Q chipset offers a

• 10 MHz to 100 MHz Input Pixel Clock Support

FPD-Link III interface with a high-speed forward

• Single Differential Pair Interconnect

channel and a bidirectional control channel for data

• Programmable Data Payload:

transmission over a single differential pair. The

DS90UB913Q/914Q chipsets incorporate differential

– 10 bit Payload up to 100Mhz

signaling on both the high-speed forward channel and

– 12 bit Payload up to 75MHz

bidirectional control channel data paths. The

• Continuous Low Latency Bidirectional Control

Serializer/ Deserializer pair is targeted for

Interface Channel with I

C support@400kHz

connections between imagers and video processors

in an ECU (Electronic Control Unit). This chipset is

• 2:1 Multiplexer to Choose Between Two Input

ideally suited for driving video data requiring up to 12

Imagers

bit pixel depth plus two synchronization signals along

• Embedded Clock With DC Balanced Coding to

with bidirectional control channel bus.

Support AC-Coupled Interconnects

There is a multiplexer at the Deserializer to choose

• Capable of Driving up to 25 Meters Shielded

between two input imagers. The Deserializer can

Twisted-pair

have only one active input imager. The primary video

• Receive Equalizer Automatically Adapts for

transport converts 10/12 bit data over a single high-

Changes in Cable Loss

speed serial stream, along with a separate low

latency bidirectional control channel transport that

• 4 Dedicated General Purpose Input (GPI)/

accepts control information from an I2C port and is

Output (GPO)

independent of video blanking period.

• LOCK Output Reporting Pin and AT-SPEED

Using TI’s embedded clock technology allows

BIST Diagnosis Feature to Validate Link

transparent full-duplex communication over a single

Integrity

differential pair, carrying asymmetrical bidirectional

• 1.8V, 2.8V or 3.3V Compatible Parallel Inputs

control channel information in both directions. This

on Serializer

single serial stream simplifies transferring a wide data

• Single Power Supply at 1.8V bus over PCB traces and cable by eliminating the

skew problems between parallel data and clock

• ISO 10605 and IEC 61000-4-2 ESD Compliant

paths. This significantly saves system cost by

• Automotive Grade Product: AEC-Q100 Grade 2

narrowing data paths that in turn reduce PCB layers,

Qualified

cable width, and connector size and pins. In addition,

the Deserializer inputs provide adaptive equalization

• Temperature Range −40°C to +105°C

to compensate for loss from the media over longer

• Small Serializer Footprint (5mm x 5mm)

distances. Internal DC balanced encoding/decoding is

• EMI/EMC Mitigation - Deserializer

used to support AC-Coupled interconnects. The

– Programmable Spread Spectrum (SSCG)

Serializer is offered in a 32-pin WQFN package and

the Deserializer is offered in a 48-pin WQFN

Outputs.

package.

– Receiver Staggered Outputs

APPLICATIONS

• Front or Rear View Camera for Collision

Mitigation

• Surround View for Parking Assistance

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (63 pages)

PAGE 1
DS90UB913Q, DS90UB914Q www.ti.com SNLS420B – JULY 2012 – REVISED APRIL 2013 DS90UB913Q/DS90UB914Q 10-100MHz 10/12- Bit DC-Balanced FPD-Link III Serializer and Deserializer with Bidirectional Control Channel Check for Samples: DS90UB913Q, DS90UB914Q FEATURES DESCRIPTION • • • The DS90UB913Q/DS90UB914Q chipset offers a FPD-Link III interface with a high-speed forward channel and a bidirectional control channel for data transmission over a single differential pair.
PAGE 2
DS90UB913Q, DS90UB914Q SNLS420B – JULY 2012 – REVISED APRIL 2013 www.ti.com Typical Application Diagram Parallel Data In 10 or 12 Parallel Data Out 10 or 12 FPD-Link III 2 Megapixel Imager/Sensor 2 HSYNC, VSYNC DS90UB913Q Bidirectional Control Bus DS90UB914Q Bidirectional Control Channel 4 GPO 2 DSP, FPGA/ µ-Processor/ ECU HSYNC, VSYNC 4 GPIO 2 Deserializer Serializer Bidirectional Control Bus Figure 1.
PAGE 3
DS90UB913Q, DS90UB914Q 20 16 15 14 VDDCML VDDD 13 DOUT+ DIN[8] 12 DOUT- DIN[9] 11 VDDT 10 VDDPLL 9 PDB DIN[7] 1 2 3 4 5 6 7 8 VSYNC PCLK SCL SDA ID[x] RES MODE DIN[11] DS90UB913Q 32-Pin WQFN (Top View) HSYNC DIN[10] DAP = GND 32 26 GPO[0] DIN[6] 27 GPO[1] 28 17 29 18 30 19 GPO[2]/ CLKOUT DIN[1] 21 GPO[3]/ CLKIN DIN[2] 22 DIN[0] DIN[3] 23 25 24 31 VDDIO DIN[4] SNLS420B – JULY 2012 – REVISED APRIL 2013 DIN[5] www.ti.
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DS90UB913Q, DS90UB914Q SNLS420B – JULY 2012 – REVISED APRIL 2013 www.ti.com DS90UB913Q SERIALIZER PIN DESCRIPTIONS (continued) Pin Name Pin No. I/O, Type Description 18 Input/Output, LVCMOS GPO3 can be configured to be the output for input signals coming from the GPIO3 pin on the Deserializer or can be configured to be the output of the local register setting on the Serializer. It can also be configured to be the input clock pin when the DS90UB913Q Serializer is working with an external oscillator.
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DS90UB913Q, DS90UB914Q VDDR IDx[0] IDx[1] RIN1- RIN1+ VDDCML1 PDB VDDIO1 GPIO[0] GPIO[1] GPIO[2] GPIO[3] 35 34 33 32 31 30 29 28 27 26 25 SNLS420B – JULY 2012 – REVISED APRIL 2013 36 www.ti.
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DS90UB913Q, DS90UB914Q SNLS420B – JULY 2012 – REVISED APRIL 2013 www.ti.com DS90UB914Q Deserializer Pin Descriptions (continued) Pin Name Pin No. MODE 37 IDx[0:1] I/O, Type Description Device mode select pin Resistor to Ground and 10 kΩ pull-up to 1.8V rail. The MODE pin on the Deserializer can be used to configure the Serializer and Deserializer to work in different input PCLK range. See details in Table 2.
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DS90UB913Q, DS90UB914Q www.ti.com SNLS420B – JULY 2012 – REVISED APRIL 2013 DS90UB914Q Deserializer Pin Descriptions (continued) Pin Name Pin No. I/O, Type 17 Power, Digital Digital Core Power, 1.8V ±5% VDDSSCG 3 Power, Analog SSCG PLL Power, 1.8V ±5% VDDR 36 Power, Analog Rx Analog Power, 1.8V ±5% 40,31 Power, Analog CML and Bidirectional control channel Drive Power, 1.8V±5% 45 Power, Analog PLL Power, 1.8V ±5% DAP Ground, DAP DAP must be grounded.
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DS90UB913Q, DS90UB914Q SNLS420B – JULY 2012 – REVISED APRIL 2013 www.ti.com Recommended Operating Conditions Min Nom Max Units Supply Voltage (VDDn) 1.71 1.8 1.89 V LVCMOS Supply Voltage (VDDIO) OR 1.71 1.8 1.89 V LVCMOS Supply Voltage (VDDIO) OR 3.0 3.3 3.6 V LVCMOS Supply Voltage (VDDIO) Only Serializer 2.52 2.8 3.08 V VDDn (1.8V) 25 mVp-p VDDIO (1.8V) 25 mVp-p VDDIO (3.
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DS90UB913Q, DS90UB914Q www.ti.com SNLS420B – JULY 2012 – REVISED APRIL 2013 Electrical Characteristics(1)(2)(3) (continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min GND VOL Low Level Output Voltage VDDIO = 1.71V to 1.
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DS90UB913Q, DS90UB914Q SNLS420B – JULY 2012 – REVISED APRIL 2013 www.ti.com Electrical Characteristics(1)(2)(3) (continued) Over recommended operating supply and temperature ranges unless otherwise specified.
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DS90UB913Q, DS90UB914Q www.ti.com SNLS420B – JULY 2012 – REVISED APRIL 2013 Electrical Characteristics(1)(2)(3) (continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol IDDIOR Parameter Deserializer (Rx) Total Supply Current (includes load current) Conditions VDDIO=1.89V CL=8pF Worst Case Pattern VDDIO=1.89V CL=8pF Random Pattern VDDIO=3.6V CL=8pF Worst Case Pattern VDDIO=3.6V CL=8pF Random Pattern VDDIO=1.89V CL=4pF Worst Case Pattern VDDIO=1.
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DS90UB913Q, DS90UB914Q SNLS420B – JULY 2012 – REVISED APRIL 2013 www.ti.com Electrical Characteristics(1)(2)(3) (continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol IDDR Parameter Conditions Deserializer (Rx) VDDn VDDn=1.89V Supply Current CL=4pF (includes load current) Worst Case Pattern VDDn=1.
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DS90UB913Q, DS90UB914Q www.ti.com SNLS420B – JULY 2012 – REVISED APRIL 2013 Serializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified.
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DS90UB913Q, DS90UB914Q SNLS420B – JULY 2012 – REVISED APRIL 2013 www.ti.com Deserializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol tRCP Parameter Receiver Output Clock Period tPDC PCLK Duty Cycle tCLH tCHL tCLH tCHL tROS tROH Conditions 10–bit mode Pin/Freq. Min 10 50 13.33 66.66 12–bit low frequency mode 10 100 PCLK 45 50 55 12–bit high frequency mode 40 50 60 12–bit low frequency mode 40 50 60 1.
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DS90UB913Q, DS90UB914Q www.ti.com SNLS420B – JULY 2012 – REVISED APRIL 2013 Deserializer Switching Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol tDCCJ fdev fmod (3) Parameter Deserializer Cycleto-Cycle Clock Jitter Spread Spectrum Clocking Deviation Frequency Conditions PCLK SSCG[3:0] = OFF (3) (1) LVCMOS Output Bus SSC[3:0] = ON (Figure 23) (1) Spread Spectrum Clocking Modulation Frequency Pin/Freq.
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DS90UB913Q, DS90UB914Q SNLS420B – JULY 2012 – REVISED APRIL 2013 www.ti.com Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I2C Compliant(1) (continued) Over recommended supply and temperature ranges unless otherwise specified Symbol Parameter Conditions Min SDA and SCL Typ GND Max 0.3*VDDIO Units VIL Input Low Level VHY Input Hysteresis VOL Output Low Level SDA, IOL=0.
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DS90UB913Q, DS90UB914Q SNLS420B – JULY 2012 – REVISED APRIL 2013 10/12, HS,VS DIN PARALLEL-TO-SERIAL www.ti.com DOUT+ RL DOUT- PCLK Figure 8. Serializer VOD Diagram Single Ended | VOS DOUTV V OD V OD+ OD- DOUT+ Differential V OD+ 0V (DOUT+)-(DOUT-) V OD- Figure 9. Serializer VOD Diagram RIN- Single Ended Vswing- Vswing+ RIN+ 0V Differential Vswing+ (RIN+)-(RIN-) 0V Vswing- Figure 10. Differential Vswing Diagram 80% VDD 80% PCLK 20% 20% tCLKT 0V tCLKT Figure 11.
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DS90UB913Q, DS90UB914Q SNLS420B – JULY 2012 – REVISED APRIL 2013 www.ti.com tTCP PCLK VDDIO/2 tDIS VDDIO/2 VDDIO/2 tDIH VDDIO DINn VDDIO/2 Setup Hold VDDIO/2 0V Figure 12. Serializer Setup/Hold Times PDB VDDIO/2 PCLK tPLD Output Active TRI-STATE DOUT± TRI-STATE SYMBOL N+2 | | SYMBOL N+1 | | SYMBOL N | | DIN | | Figure 13.
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DS90UB913Q, DS90UB914Q SYMBOL N + 2 SYMBOL N + 3 SYMBOL N + 3 | | 0V | | SYMBOL N + 1 | | SYMBOL N RIN± | | SNLS420B – JULY 2012 – REVISED APRIL 2013 | | www.ti.com tDD PCLK SYMBOL N - 1 | || SYMBOL N - 2 | || | || SYMBOL N - 3 | || | || ROUTn VDDIO/2 SYMBOL N SYMBOL N+1 Figure 17. Deserializer Delay tRCP PCLK VDDIO 1/2 VDDIO 1/2 VDDIO 0V VDDIO ROUT[n], VS, HS 1/2 VDDIO 1/2 VDDIO 0V tROS tROH Figure 18.
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DS90UB913Q, DS90UB914Q SNLS420B – JULY 2012 – REVISED APRIL 2013 www.ti.com PDB= H OEN VIH VIL VIH OSS_SEL VIL RIN (Diff.) 'RQ¶W &DUH tSEH tONS LOCK TRI-STATE TRI-STATE PASS tSES tONH LOW ACTIVE HIGH ROUT[0:11], HS, VS TRI-STATE LOW PCLK (RFB = L) TRI-STATE LOW TRI-STATE LOW HIGH HIGH ACTIVE ACTIVE LOW TRI-STATE LOW TRI-STATE Figure 20. Output State (Setup and Hold) Times 4 2 JITTER TRANSFER (dB) 0 -2 -4 -6 -8 -10 -12 -14 - 16 - 18 1.0E+04 1.0E+05 1.0E+06 1.
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DS90UB913Q, DS90UB914Q www.ti.com SNLS420B – JULY 2012 – REVISED APRIL 2013 JITTER AMPLITUDE (UI) 0.65 0.60 0.55 0.50 0.45 1E+04 1E+05 1E+06 1E+07 JITTER FREQUENCY (Hz) Figure 22. Typical Deserializer Input Jitter Tolerance Curve at 1.4Gbps Line Rate Frequency fdev (max) FPCLK+ fdev FPCLK fdev (min) FPCLK- Time 1 / fmod Figure 23.
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DS90UB913Q, DS90UB914Q SNLS420B – JULY 2012 – REVISED APRIL 2013 www.ti.com Table 1.
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DS90UB913Q, DS90UB914Q www.ti.com SNLS420B – JULY 2012 – REVISED APRIL 2013 Table 1. DS90UB913Q Control Registers (continued) Addr (Hex) Name Bits Field R/W Default 7 RX CRC Checker Enable RW 1 Back-channel CRC Checker Enable 1:Enabled 0:Disabled 6 TX Parity Generator Enable RW 1 Forward channel Parity Generator Enable 1: Enable 0: Disable 0 Clear CRC Error Counters. This bit is NOT self-clearing.
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DS90UB913Q, DS90UB914Q SNLS420B – JULY 2012 – REVISED APRIL 2013 www.ti.com Table 1. DS90UB913Q Control Registers (continued) Addr (Hex) 0x06 0x07 Name Bits Desializer Device ID 0 Freeze Device ID RW Default DESAlias 7:1 SlaveID 7:1 SlaveAlias 7:1 0 Deserializer ALIAS ID RW RW Description 0x00 7-bit Deserializer Device ID Configures the I2C Slave ID of the remote Deserializer. A value of 0 in this field disables I2C access to the remote Deserializer.
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DS90UB913Q, DS90UB914Q www.ti.com SNLS420B – JULY 2012 – REVISED APRIL 2013 Table 1. DS90UB913Q Control Registers (continued) Addr (Hex) 0x0D 0x0E Name GPO[0] and GPO[1] Configuration GPO[2] and GPO[3] Configuration Bits Field R/W Default 7 GPO1 Output Value RW 0 Local GPIO Output Value This value is output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is Output, and remote GPIO control is disabled.
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DS90UB913Q, DS90UB914Q SNLS420B – JULY 2012 – REVISED APRIL 2013 www.ti.com Table 1. DS90UB913Q Control Registers (continued) Addr (Hex) Name Bits Field 7:5 RSVD Reserved SDA Output Delay 00 SDA Output Delay This field configures output delay on the SDA output. Setting this value will increase output delay in units of 50ns.
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DS90UB913Q, DS90UB914Q www.ti.com SNLS420B – JULY 2012 – REVISED APRIL 2013 Table 1. DS90UB913Q Control Registers (continued) Addr (Hex) Name Bits Field 7:3 RSVD Reserved Clock Source Allows choosing different OSC clock frequencies for forward channel frame. OSC Clock Frequency in Functional Mode when OSC mode is selected or when the selected clock source is not present e.g. missing PCLK/ External Oscillator. See Table 3 for oscillator clock frequencies when PCLK/ External Clock is missing.
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DS90UB913Q, DS90UB914Q SNLS420B – JULY 2012 – REVISED APRIL 2013 www.ti.com Table 2. DS90UB914Q Control Registers (continued) Addr (Hex) Name Bits 7:6 5 4:2 0x01 0x02 R/W Default Description RSVD Reserved ANAPWDN This register can be set only through local I2C access 1: Analog power-down : Powers Down the analog block in the Serializer 0: No effect RW 0 RSVD Reserved Reset 1 Digital Reset 1 RW 0 Digital Reset Resets the entire digital block except registers. This bit is self-clearing.
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DS90UB913Q, DS90UB914Q www.ti.com SNLS420B – JULY 2012 – REVISED APRIL 2013 Table 2. DS90UB914Q Control Registers (continued) Addr (Hex) Name Bits Field R/W Default 7 RX Parity Checker Enable RW 1 Forward Channel Parity Checker Enable 1: Enable 0: Disable 6 TX CRC Checker Enable RW 1 Back Channel CRC Generator Enable 1: Enable 0: Disable 5 VDDIO Control RW 1 Auto voltage control 1: Enable (auto detect mode) 0: Disable 4 VDDIO Mode RW 0 VDDIO voltage set 1: 3.3V 0: 1.
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DS90UB913Q, DS90UB914Q SNLS420B – JULY 2012 – REVISED APRIL 2013 www.ti.com Table 2. DS90UB914Q Control Registers (continued) Addr (Hex) 0x08 Name Slave ID[0] Bits 7:1 0 0x09 Slave ID[1] 7:1 0 0x0A Slave ID[2] 7:1 0 0x0B Slave ID[3] 7:1 0 0x0C Slave ID[4] 7:1 0 0x0D Slave ID[5] 7:1 0 30 Field Slave ID0 R/W RW Default Description 0 7-bit Remote Slave Device ID 0 Configures the physical I2C address of the remote I2C Slave device attached to the remote Serializer.
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DS90UB913Q, DS90UB914Q www.ti.com SNLS420B – JULY 2012 – REVISED APRIL 2013 Table 2. DS90UB914Q Control Registers (continued) Addr (Hex) 0x0E Name Slave ID[6] Bits 7:1 0 0x0F Slave ID[7] 7:1 0 0x10 Slave Alias[0] 7:1 0 0x11 Slave Alias[1] 7:1 0 0x12 Slave Alias[2] 7:1 0 0x13 Slave Alias[3] 7:1 0 Field Slave ID6 R/W RW Default Description 0 7-bit Remote Slave Device ID 6 Configures the physical I2C address of the remote I2C Slave device attached to the remote Serializer.
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DS90UB913Q, DS90UB914Q SNLS420B – JULY 2012 – REVISED APRIL 2013 www.ti.com Table 2.
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DS90UB913Q, DS90UB914Q www.ti.com SNLS420B – JULY 2012 – REVISED APRIL 2013 Table 2.
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DS90UB913Q, DS90UB914Q SNLS420B – JULY 2012 – REVISED APRIL 2013 www.ti.com Table 2.
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DS90UB913Q, DS90UB914Q www.ti.com SNLS420B – JULY 2012 – REVISED APRIL 2013 Table 2. DS90UB914Q Control Registers (continued) Addr (Hex) Name Bits R/W Default Description Control Channel Sequence Error Detected This bit indicates a sequence error has been detected in forward control channel.
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DS90UB913Q, DS90UB914Q SNLS420B – JULY 2012 – REVISED APRIL 2013 www.ti.com Table 2. DS90UB914Q Control Registers (continued) Addr (Hex) Name Bits 7:2 Oscillator output divider select 0x3C 1:0 Field R/W Reserved OSC OUT DIVIDER SEL Selects the divider for the OSC clock out on PCLK when system is not locked and selected by OEN/OSSSEL 0x02[5] 00: 50M (+/- 30%) 01: 25M (+/- 30%) 1X: 12.
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DS90UB913Q, DS90UB914Q www.ti.com SNLS420B – JULY 2012 – REVISED APRIL 2013 Table 4. BIST Clock Sources DS90UB914Q Reg 0x24 [2:1] 10–bit Mode 12–bit High Frequency Mode 12–bit Low Frequency Mode 00 PCLK PCLK PCLK 01 100 MHz 75 MHz 50 MHz 10 50 MHz 37.5 MHz 25 MHz 11 25MHz 18.75 MHz 12.5 MHz Functional Description The DS90UB913/914Q FPD- Link III chipsets are intended to link mega-pixel camera imagers and video processors in ECUs.
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DS90UB913Q, DS90UB914Q SNLS420B – JULY 2012 – REVISED APRIL 2013 www.ti.
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DS90UB913Q, DS90UB914Q www.ti.
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DS90UB913Q, DS90UB914Q SNLS420B – JULY 2012 – REVISED APRIL 2013 www.ti.com MODE Pin on Deserializer The mode pin on the Deserializer can be used to configure the device to work in the 12-bit low frequency mode, 12- bit high frequency mode or the 10 bit mode of operation. Internally, the DS90UB913/914Q chipset operates in a divide-by-1 mode in the 12- bit low frequency mode, divide-by-2 mode in the 10-bit mode and a divide-by-1.5 mode in the 12- bit high frequency mode. The pin must be pulled to VDD (1.
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DS90UB913Q, DS90UB914Q www.ti.com SNLS420B – JULY 2012 – REVISED APRIL 2013 Serializer A DS90UB913Q Camera A DATA PCLK DATA PCLK 2 I C Serializer B DS90UB913Q Camera B CMOS Image Sensor GPIO GPIO FSYNC 2:1 CMOS Image Sensor DS90UB914Q FSYNC 2 I C Deserializer A ECU Module DATA PCLK GPIO FSYNC 2 I C Serializer B PC Figure 28.
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DS90UB913Q, DS90UB914Q Bus Activity: Master SDA Line Register Address Slave Address 7-bit Address S Stop www.ti.com Start SNLS420B – JULY 2012 – REVISED APRIL 2013 Data P 0 A C K A C K A C K Bus Activity: Slave S Register Address Slave Address 7-bit Address A C K Bus Activity: Slave Slave Address S 0 N A C K 7-bit Address A C K Stop SDA Line Start Bus Activity: Master Start Figure 29. Write Byte P 1 A C K Data Figure 30.
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DS90UB913Q, DS90UB914Q www.ti.com SNLS420B – JULY 2012 – REVISED APRIL 2013 I2C Pass Through I2C pass-through provides an alternative means to independently address slave devices. The mode enables or disables I2C bidirectional control channel communication to the remote I2C bus. This option is used to determine whether or not an I2C instruction is to be transferred over to the remote I2C device.
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DS90UB913Q, DS90UB914Q SNLS420B – JULY 2012 – REVISED APRIL 2013 www.ti.com 1.8V 10k VDDIO ID[x] RPU RPU RID HOST DS90UB913Q SCL SCL SDA SDA To other Devices Figure 34. ID[x] Address Decoder on the Serializer Table 7. ID[x] Resistor Value for DS90UB913Q Serializer ID[x] Resistor Value — DS90UB913Q Serializer Resistor RID0 Ω (1% Tolerance) Address 7'b Address 8'b 0 appended (WRITE) 0k 0x58 0xB0 2k 0x59 0xB2 4.7k 0x5A 0xB4 8.
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DS90UB913Q, DS90UB914Q www.ti.com SNLS420B – JULY 2012 – REVISED APRIL 2013 1.8V 1.8V 10k 10k RID1 RID0 VDDIO IDx[0] RPU IDx[1] RPU HOST DS90UB914Q SCL SCL SDA SDA To other Devices Figure 35. ID[x[ Address Decoder on the Deserializer Table 8.
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DS90UB913Q, DS90UB914Q SNLS420B – JULY 2012 – REVISED APRIL 2013 www.ti.com Table 9.
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DS90UB913Q, DS90UB914Q www.ti.
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DS90UB913Q, DS90UB914Q SNLS420B – JULY 2012 – REVISED APRIL 2013 www.ti.com DS90UB913Q Camera A CMOS Image Sensor DS90UB914Q DATA PCLK DATA PCLK 2 I C Serializer A FSYNC FSO GPIO GPO FSIN FSYNC 2 I C Deserializer A ECU Module Camera B CMOS Image Sensor DS90UB913Q DS90UB914Q DATA PCLK DATA PCLK 2 I C Serializer B FSYNC FSO GPIO GPO FSIN FSYNC 2 PC I C Deserializer B Figure 37.
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DS90UB913Q, DS90UB914Q www.ti.com SNLS420B – JULY 2012 – REVISED APRIL 2013 Deserializer – Adaptive Input Equalization(AEQ) The receiver inputs provide an adaptive input equalization filter in order to compensate for loss from the media. The level of equalization can also be manually selected via register controls. The fully adaptive equalizer output can be seen using the CMLOUTP/CMLOUTN pins in the Deserializer.
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DS90UB913Q, DS90UB914Q SNLS420B – JULY 2012 – REVISED APRIL 2013 www.ti.com PCLK DIN/ ROUT TRFB/RRFB: 0 TRFB/RRFB: 1 Figure 40. Programmable PCLK Strobe Select Power Up Requirements and PDB Pin It is required to delay and release the PDB Signal after VDD (VDDn and VDDIO) power supplies have settled to the recommended operating voltage. An external RC network can be connected to the PDB pin to ensure PDB arrives after all the VDD has stabilized.
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DS90UB913Q, DS90UB914Q www.ti.com SNLS420B – JULY 2012 – REVISED APRIL 2013 Step2. The DS90UB913Q Serializer is woken up through the back channel if it is not already on. The SSO pattern on the data pins is send through the FPD-Link III to the deserializer. Once the serializer and deserializer are in the BIST mode and the deserializer acquires Lock, the PASS pin of the deserializer goes high and BIST starts checking data stream.
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DS90UB913Q, DS90UB914Q SNLS420B – JULY 2012 – REVISED APRIL 2013 www.ti.com APPLICATIONS INFORMATION AC COUPLING The SER/DES supports only AC-coupled interconnects through an integrated DC balanced decoding scheme. External AC coupling capacitors must be placed in series in the FPD-Link III signal path as illustrated in Figure 43. DOUT+ RIN+ DOUT- RIN- D R Figure 43.
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DS90UB913Q, DS90UB914Q www.ti.com SNLS420B – JULY 2012 – REVISED APRIL 2013 Figure 45 shows the typical connection of a DS90UB913Q Serializer DS90UB913Q (SER) VDDIO VDDIO C3 1.8V VDDT C4 C8 C9 C13 1.8V DIN0 DIN1 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 DIN8 DIN9 DIN10 DIN11 HS VS PCLK LVCMOS Parallel Bus 1.8V VDDPLL C5 C14 C10 FB1 1.8V VDDCML C6 C11 C15 C7 C12 FB2 1.8V VDDD C1 Serial FPD-Link III Interface DOUT+ DOUTC2 10 k: MODE 1.
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DS90UB913Q, DS90UB914Q SNLS420B – JULY 2012 – REVISED APRIL 2013 www.ti.com Figure 46 shows a typical connection of the DS90UB914Q Deserializer. DS90UB914Q (Des) 1.8V VDDD C3 C11 C4 C12 C5 C13 VDDIO VDDIO1 C8 VDDR C16 C18 VDDIO2 C9 VDDSSCG VDDIO3 C10 1.8V VDDPLL FB1 C6 C14 C17 FB2 C7 C15 C19 1.8V VDDCML C1 RIN1+ Serial FPD-Link II Interface RIN1- C2 RIN0+ C1 RIN0- C2 1.
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DS90UB913Q, DS90UB914Q www.ti.com SNLS420B – JULY 2012 – REVISED APRIL 2013 PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS Circuit board layout and stack-up for the Ser/Des devices should be designed to provide low-noise power feed to the device. Good layout practice will also separate high frequency or high-level inputs and outputs to minimize unwanted stray noise pickup, feedback and interference.
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DS90UB913Q, DS90UB914Q SNLS420B – JULY 2012 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision A (April 2013) to Revision B • 56 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 17-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing DS90UB913QSQ/NOPB WQFN RTV 32 DS90UB913QSQE/NOPB WQFN RTV DS90UB913QSQX/NOPB WQFN RTV DS90UB914QSQ/NOPB WQFN DS90UB914QSQE/NOPB DS90UB914QSQX/NOPB SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1 32 250 178.0 12.4 5.3 5.3 1.3 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS90UB913QSQ/NOPB WQFN RTV 32 1000 213.0 191.0 55.0 DS90UB913QSQE/NOPB WQFN RTV 32 250 213.0 191.0 55.0 DS90UB913QSQX/NOPB WQFN RTV 32 4500 367.0 367.0 35.0 DS90UB914QSQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 DS90UB914QSQE/NOPB WQFN RHS 48 250 213.0 191.0 55.
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MECHANICAL DATA RHS0048A SQA48A (Rev B) www.ti.
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MECHANICAL DATA RTV0032A SQA32A (Rev B) www.ti.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.