Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - deserialisers LVCMOS WQFN 60

DS90UH926Q

www.ti.com

SNLS337J –OCTOBER 2010–REVISED APRIL 2013

DS90UH926Q 720p 24-bit Color FPD-Link III Deserializer with HDCP

Check for Samples: DS90UH926Q

FEATURES

DESCRIPTION

The DS90UH926Q deserializer, in conjunction with

• Integrated HDCP Cipher Engine with On-Chip

the DS90UH925Q serializer, provides a solution for

Key Storage

secure distribution of content-protected digital video

• Bidirectional Control Interface Channel

within automotive entertainment systems. This

Interface with I2C Compatible Serial Control

chipset translates a parallel RGB Video Interface into

Bus

a single pair high-speed serialized interface. The

digital video data is protected using the industry

• Supports High Definition (720p) Digital Video

standard HDCP copy protection scheme. The serial

Format

bus scheme, FPD-Link III, supports full duplex of high

• RGB888 + VS, HS, DE and Synchronized I2S

speed forward data transmission and low speed

Audio Supported

backchannel communication over a single differential

• 5 to 85 MHz PCLK Supported

link. Consolidation of video data and control over a

single differential pair reduces the interconnect size

• Single 3.3V Operation with 1.8V or 3.3V

and weight, while also eliminating skew issues and

compatible LVCMOS I/O Interface

simplifying system design.

• AC-coupled STP Interconnect up to 10 Meters

The DS90UH926Q deserializer recovers the RGB

• Parallel LVCMOS Video Outputs

data, three video control signals and four

• I2C Compatible Serial Control Bus for

synchronized I2S audio signals. It extracts the clock

Configuration

from a high speed serial stream. An output LOCK pin

provides the link status if the incoming data stream is

• DC-Balanced & Scrambled Data w/ Embedded

locked, without the use of a training sequence or

Clock

special SYNC patterns, as well as a reference clock.

• Adaptive Cable Equalization

The DS90UH926Q deserializer has a 31-bit parallel

• Supports HDCP Repeater Application

LVCMOS output interface to accommodate the RGB,

• @ SPEED Link BIST Mode and LOCK Status

video control, and audio data.

An adaptive equalizer optimizes the maximum cable

• Image Enhancement (White Balance and

reach. EMI is minimized by output SSC generation

Dithering) and Internal Pattern Generation

(SSCG) and Enhanced Progressive Turn-On (EPTO)

• EMI Minimization (SSCG and EPTO)

features.

• Low Power Modes Minimize Power Dissipation

The HDCP cipher engine is implemented in both the

• Automotive Grade Product: AEC-Q100 Grade 2

serializer and deserializer. HDCP keys are stored in

on-chip memory.

qualified

• >8kV HBM and ISO 10605 ESD rating

• Backward Compatible Modes

APPLICATIONS

• Automotive Display for Navigation

• Rear Seat Entertainment Systems

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (56 pages)

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DS90UH926Q www.ti.com SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 DS90UH926Q 720p 24-bit Color FPD-Link III Deserializer with HDCP Check for Samples: DS90UH926Q FEATURES DESCRIPTION • The DS90UH926Q deserializer, in conjunction with the DS90UH925Q serializer, provides a solution for secure distribution of content-protected digital video within automotive entertainment systems. This chipset translates a parallel RGB Video Interface into a single pair high-speed serialized interface.
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DS90UH926Q SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 www.ti.com Applications Diagram HOST Graphics Processor RGB Digital Display Interface VDD33 VDDIO (1.8V or 3.3V) (3.3V) R[7:0] G[7:0] B[7:0] HS VS DE PCLK R[7:0] G[7:0] B[7:0] HS VS DE PCLK FPD-Link III 1 Pair / AC Coupled 0.1 PF 0.1 PF DOUT+ RIN+ DOUT- RIN100 ohm STP Cable PDB OSS_SEL OEN MODE_SEL MODE_SEL INTB INTB_IN DS90UH925Q Serializer PDB I2S AUDIO (STEREO) VDDIO VDD33 (3.3V) (1.8V or 3.
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DS90UH926Q www.ti.
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DS90UH926Q SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS (continued) Pin Name Pin # I/O, Type BISTEN 44 I, LVCMOS w/ pull-down Description BIST Enable Pin. 0: BIST Mode is disabled. 1: BIST Mode is enabled. BISTC 16 I, LVCMOS w/ pull-down BIST Clock Select. Shared with INTB_IN 0: PCLK; 1: 33 MHz IDx 56 I, Analog SCL 3 I/O, LVCMOS Open Drain I2C Clock Input / Output Interface Must have an external pull-up to VDD33, DO NOT FLOAT. Recommended pull-up: 4.7kΩ.
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DS90UH926Q www.ti.
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DS90UH926Q SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) −0.3V to +4.0V Supply Voltage – VDD33 −0.3V to +4.0V Supply Voltage – VDDIO −0.3V to (VDDIO + 0.3V) LVCMOS I/O Voltage −0.3V to +2.
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DS90UH926Q www.ti.com SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 Recommended Operating Conditions Min Nom Max Units Supply Voltage (VDD33) 3.0 3.3 3.6 V LVCMOS Supply Voltage (VDDIO) 3.0 3.3 3.6 V OR LVCMOS Supply Voltage (VDDIO) 1.71 1.8 1.89 V Operating Free Air Temperature (TA) −40 +25 +105 °C 85 MHz 100 mVP-P PCLK Frequency Supply Noise (1) 5 (1) Supply noise testing was done with minimum capacitors on the PCB.
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DS90UH926Q SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 www.ti.com DC Electrical Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3) Symb ol Parameter Conditions Pin/Freq. Min Typ Max Units +50 mV FPD-LINK III CML RECEIVER INPUT DC SPECIFICATIONS VTH Differential Threshold High Voltage VTL Differential Threshold Low Voltage VCM Differential Commonmode Voltage RT Internal Termination Resistor - Differential VCM = 2.
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DS90UH926Q www.ti.com SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 AC Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3) Symbol Parameter Conditions Pin/Freq. Min Typ Max Units f = 5 – 85MHz, GPIO[3:0] 0.25*f Mbps >50 >75 kbps 0.3 0.
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DS90UH926Q SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 www.ti.com AC Electrical Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified.
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DS90UH926Q www.ti.com SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 Recommended Timing for the Serial Control Bus Over 3.3V supply and temperature ranges unless otherwise specified. Symbol fSCL Parameter SCL Clock Frequency tLOW tHIGH tHD;STA tSU:STA tHD;DAT tSU;DAT tSU;STO tBUF tr tf Conditions Min Typ Max Units Standard Mode 0 100 kHz Fast Mode 0 400 kHz Standard Mode 4.7 µs Fast Mode 1.3 µs Standard Mode 4.0 µs Fast Mode 0.
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DS90UH926Q SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 www.ti.com AC TIMING DIAGRAMS AND TEST CIRCUITS VDDIO PCLK GND VDDIO RGB[n] (odd), VS, HS GND VDDIO RGB[n] (even), DE GND Figure 2. Checker Board Data Pattern EW VOD (+) CMLOUT (Diff.) EH 0V EH VOD (-) tBIT (1 UI) Figure 3. CML Output Driver VDDIO 80% 20% GND tCLH tCHL Figure 4. LVCMOS Transition Times START BIT STOP BIT START BIT STOP BIT RIN (Diff.
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DS90UH926Q www.ti.com SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 2.0V PDB 0.8V RIN (Diff.) }v[š Œ tDDLT LOCK TRI-STATE or LOW Z or L tXZR RGB[7:0], HS, VS, DE, I2S TRI-STATE or LOW or Pulled Up PCLK (RFB = L) Z or L or PU TRI-STATE or LOW OFF Z or L IN LOCK TIME ACTIVE OFF Figure 6. PLL Lock Times and PDB TRI-STATE Delay VDDIO PCLK w/RFB = H 1/2 VDDIO GND RGB[7:0], VS, HS, DE, I2S VDDIO VOHmin VOLmax tROS GND tROH Figure 7.
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DS90UH926Q SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 www.ti.com PDB = H VIH OSS_SEL VIL VIH OEN VIL RIN (Diff.) }v[š Œ tSEH tSES tONH tONS TRI-STATE LOCK (HIGH) PASS ACTIVE HIGH RGB[7:0], HS, VS, DE, I2S[2:0] LOW TRI-STATE PCLK (RFB = L) LOW TRI-STATE HIGH ACTIVE ACTIVE TRI-STATE LOW TRI-STATE LOW Figure 8. Output State (Setup and Hold) Times BISTEN 1/2 VDDIO tPASS PASS (w/errors) 1/2 VDDIO Current BIST Test - Toggle on Error Prior BIST Result Result Held Figure 9.
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DS90UH926Q www.ti.com SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 Functional Description The DS90UH926Q deserializer receives a 35-bits symbol over a single serial FPD-Link III pair operating upto 2.975 Gbps application payload. The serial stream contains an embedded clock, video control signals and the DC-balanced video data and audio data which enhance signal quality to support AC coupling.
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DS90UH926Q SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 www.ti.com COMMON MODE FILTER PIN (CMF) The deserializer provides access to the center tap of the internal termination. A capacitor must be placed on this pin for additional common-mode filtering of the differential pair. This can be useful in high noise environments for additional noise rejection capability. A 0.1 μF capacitor has to be connected to this pin to Ground.
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DS90UH926Q www.ti.com SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 Table 1. SSCG Configuration LFMODE = L (15 - 85 MHz) SSCG Configuration (0x2C) LFMODE = L (15 - 85MHz) Spread Spectrum Output SSC[2] SSC[1] SSC[0] Fdev (%) Fmod (kHz) L L L ±0.9 PCLK / 2168 L L H ±1.2 L H L ±1.9 L H H ±2.5 H L L ±0.7 H L H ±1.3 H H L ±2.0 H H H ±2.5 PCLK / 1300 Table 2.
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DS90UH926Q SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 www.ti.com SERIAL LINK FAULT DETECT The serial link fault detection is able to detect any of following seven (7) conditions 1. cable open 2. “+” to “-“ short 3. “+” short to GND 4. “-“ short to GND 5. “+” short to battery 6. “-“ short to battery 7. Cable is linked incorrectly If any one of the fault conditions occurs, The Link Detect Status is 0 (cable is not detected) on the Serial Control Bus Register bit 0 of address 0x1C Table 9.
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DS90UH926Q www.ti.com SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 INTERRUPT PIN — FUNCTIONAL DESCRIPTION AND USAGE (INTB) 1. On DS90UH925, set register 0xC6[5] = 1 and 0xC6[0] = 1 2. DS90UH926Q deserializer INTB_IN (pin 16) is set LOW by some downstream device. 3. DS90UH925Q serializer pulls INTB (pin 31) LOW. The signal is active low, so a LOW indicates an interrupt condition. 4. External controller detects INTB = LOW; to determine interrupt source, read HDCP_ISR register . 5.
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DS90UH926Q SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 www.ti.com I2S RECEIVING In normal 24-bit RGB operation mode, the DS90UH926Q provides up to 3-bit of I2S. They are I2S_CLK, I2S_WC and I2S_DA, as well as the Master I2S Clock (MCLK). The encrypted and packetized audio information is received during the video blanking periods along with specific information about the clock frequency. Note: The bit rates of any I2S input bits must maintain one fourth of the PCLK rate.
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DS90UH926Q www.ti.com SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 Table 5. Audio Interface Frequencies (continued) Sample Rate (kHz) I2S Data Word Size (bits) I2S CLK (MHz) MCLK Output (MHz) Bit [6:4] (Address 0x3A) 96 24 4.
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DS90UH926Q SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 www.ti.com GPO_REG[8:4] Enable Sequence GPO_REG[8:4] are the outputs only pins. They must be programmed through the local register bits. See Table 7 for the GPO_REG enable sequencing. Step 1: Enable the 18-bit mode either through the configuration register bit Table 9 on DS90UH925Q only. DS90UH926Q is automatically configured as in the 18-bit mode. Step 2: To enable GPO_REG8 outputs an “1” , write 0x90 to address 0x21 on DS90UH926Q.. Table 7.
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DS90UH926Q www.ti.com SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 HDCP The Cipher function is implemented in the deserializer per HDCP v1.3 specification. It supports the HDCP key exchange for the authentication over the back channel with the DS90UH925Q serializer. An on-chip Non-Volatile Memory (NVM) is used to store the HDCP keys. The confidential HDCP keys are loaded by TI during the manufacturing process and are not accessible external to the device.
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DS90UH926Q SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 www.ti.com To support HDCP Repeater operation, the DS90UH926Q Deserializer includes the ability to control the downstream authentication process, assemble the KSV list for downstream HDCP Receivers, and pass the KSV list to the upstream HDCP Transmitter. An I2C master within the DS90UH926Q communicates with the I2C slave within the DS90UH925Q Serializer.
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DS90UH926Q www.ti.com SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 DS90UH926Q VDD33 DS90UH925Q R[7:0] R[7:0] G[7:0] G[7:0] B[7:0] B[7:0] DE DE VS VS HS HS I2S_CLK I2S_CLK I2S_WC I2S_WC I2S_DA I2S_DA Optional MODE_SEL VDD33 MODE_SEL VDDIO INTB_IN INTB VDD33 VDD33 ID[x] VDD33 SDA SDA SCL SCL ID[x] Figure 17.
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DS90UH926Q SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 www.ti.com Step 2: The DS90UH925Q serializer is woken up through the back channel if it is not already on. The all zero pattern on the data pins is sent through the FPD-Link III to the deserializer. Once the serializer and the deserializer are in BIST mode and the deserializer acquires Lock, the PASS pin of the deserializer goes high and BIST starts checking the data stream.
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DS90UH926Q www.ti.com SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 DES Outputs BISTEN (DES) Case 1 - Pass PCLK (RFB = L) RGB[7:0] HS, VS, DE DATA (internal) PASS Prior Result PASS PASS X X X FAIL Prior Result Normal SSO Case 2 - Fail X = bit error(s) DATA (internal) BIST Test BIST Duration BIST Result Held Normal Figure 19.
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DS90UH926Q SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 www.ti.com Serial Control Bus The DS90UH926Q is configured by the use of a serial control bus that is I2C protocol compatible. . Multiple deserializer devices may share the serial control bus since 16 device addresses are supported. Device address is set via R1 and R2 values on IDx pin. See Figure 20 below. The serial control bus consists of two signals and a configuration pin. The SCL is a Serial Bus Clock Input / Output.
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DS90UH926Q www.ti.com SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 Table 9.
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DS90UH926Q SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 www.ti.com Table 9. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) Register Name 3 0x03 Configuration [1] Bit(s) Register Type 7 6 Default Function (hex) 0xF0 Reserved.
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DS90UH926Q www.ti.com SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 Table 9. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) Register Name 6 0x06 I2C Control [2] Bit(s) Register Type 7 R 6 Default Function (hex) 0x00 Forward Channel Sequence Error Control Channel Sequence Error Detected It indicates a sequence error has been detected in forward control channel. It this bit is set, an error may have occurred in the control channel operation.
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DS90UH926Q SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 www.ti.com Table 9.
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DS90UH926Q www.ti.com SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 Table 9.
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DS90UH926Q SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 www.ti.com Table 9.
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DS90UH926Q www.ti.com SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 Table 9. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) Register Name 31 0x1F GPO_REG4 and GPO3 Config Bit(s) Register Type 7 RW Default Function (hex) 0x00 GPO_REG4 Local GPO_REG4 Output Value Output This value is output on the GPO when the GPO function is Value enabled, the local GPO direction is Output, and remote GPO control is disabled.
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DS90UH926Q SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 www.ti.com Table 9. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) Register Name Bit(s) Register Type 34 0x22 Data Path Control 7 RW 6 RW Pass RGB Setting this bit causes RGB data to be sent independent of DE. This allows operation in systems which may not use DE to frame video data or send other data when DE is deasserted. Note that setting this bit prevents HDCP operation and blocks packetized audio.
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DS90UH926Q www.ti.com SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 Table 9.
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DS90UH926Q SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 www.ti.com Table 9. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) Register Name 43 0x2B I2S Control Bit(s) Register Type 7 RW Default Function (hex) 0x00 I2S PLL 6:1 0 44 58 0x2C 0x3A SSCG Control I2S MCLK Output 38 0x41 Link Error Count I2S PLL Control 0: I2S PLL is ON for I2S data jitter cleaning 1: I2S PLL is OFF.
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DS90UH926Q www.ti.com SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 Table 9. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) Register Name 68 0x44 Equalization Bit(s) Register Type 7:5 RW Default Function (hex) 0x60 EQ Stage 1 Select 4 86 0x56 CML Output Reserved RW EQ Stage 2 Select EQ select value. Used if adaptive EQ is bypassed.
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DS90UH926Q SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 www.ti.com Table 9. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) Register Name 101 0x65 Pattern Generator Configuration Bit(s) Register Type 7:5 Default Function (hex) 0x00 Descriptions Reserved 4 RW Pattern Generator 18 Bits 18-bit Mode Select 1: Enable 18-bit color pattern generation. Scaled patterns will have 64 levels of brightness and the R, G, and B outputs use the six most significant color bits.
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DS90UH926Q www.ti.com SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 Table 9. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) Register Name 192 0xC0 HDCP_DBG 193 0xC1 HDCP_DBG2 Bit(s) Register Type 7:4 Default Function (hex) 0x00 Reserved 3 R RGB_CHK SUM_EN Enable RBG video line checksum. 1: Enables sending of ones-complement checksum for each 8-bit RBG data channel following end of each video data line.
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DS90UH926Q SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 www.ti.com Table 9. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) Register Name 227 0xE3 RPTR TX3 Register Type 7:1 R 0 R Default Function (hex) 0x00 Descriptions HDCP Serializer Port 3 Address Serializer Port 3 I2C Address: Indicates the I2C address for the Repeater Serializer Port.
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DS90UH926Q www.ti.com SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 Image Enhancement Features Several image enhancement features are provided. White balance LUTs allow the user to define and target the color temperature of the display. Adaptive Hi-FRC dithering enables the presentation of “true-color” images on an 18–bit color display. WHITE BALANCE The White Balance feature enables similar display appearance when using LCD’s from different vendors.
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DS90UH926Q SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 www.ti.com Enabling white balance The user must load all 3 LUTs prior to enabling the white balance feature. The following sequence must be followed by the user. To initialize white balance after power-on (Table 10): 1. Load contents of all 3 LUTs . This requires a sequential loading of LUTs - first RED, second GREEN, third BLUE. 256, 8-bit entries must be loaded to each LUT. Page registers must be set to select each LUT. 2. Enable white balance.
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DS90UH926Q www.ti.com SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 Table 10.
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DS90UH926Q SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 www.ti.
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DS90UH926Q www.ti.com SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 APPLICATIONS INFORMATION DISPLAY APPLICATION The DS90UH926Q, in conjunction with the DS90UH925Q, is intended for interface between a HDCP compliant host (graphics processor) and a Display. It supports an 24-bit color depth (RGB888) and high definition (720p) digital video format.
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DS90UH926Q SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 www.ti.com DS90UH926Q 3.3V 3.3V/1.8V VDDIO VDD33_A FB1 C6 FB2 C4 VDDIO VDD33_B C7 C5 VDDIO C8 CAPP12 C9 CAPR12 C13 CAPI2S PASS C10 LOCK R7 R6 R5 R4 R3 R2 R1 R0 CAPL12 C11 C12 C1 Serial FPD-Link III Interface RIN+ RINC2 CMF G7 G6 G5 G4 G3 G2 G1 G0 C3 CMLOUTP 100: VDD33_B* CMLOUTN R5 OSS_SEL OEN BISTEN Host Control BISTC / INTB_IN PDB C14 4.7k 4.
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DS90UH926Q www.ti.com SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 TRANSMISSION MEDIA The DS90UH925Q and DS90UH926Q chipset is intended to be used in a point-to-point configuration through a shielded twisted pair cable. The serializer and deserializer provide internal termination to minimize impedance discontinuities. The interconnect (cable and connector) between the serializer and deserializer should have a differential impedance of 100 Ω.
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DS90UH926Q SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 www.ti.com CML INTERCONNECT GUIDELINES See AN-1108 (SNLA008) and AN-905 (SNLA035) for full details.
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DS90UH926Q www.ti.com SNLS337J – OCTOBER 2010 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision I (April 2013) to Revision J • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device DS90UH926QSQ/NOPB Package Package Pins Type Drawing WQFN NKB 60 DS90UH926QSQE/NOPB WQFN NKB DS90UH926QSQX/NOPB WQFN NKB SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 330.0 16.4 9.3 9.3 1.3 12.0 16.0 Q1 60 250 178.0 16.4 9.3 9.3 1.3 12.0 16.0 Q1 60 2000 330.0 16.4 9.3 9.3 1.3 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS90UH926QSQ/NOPB WQFN NKB 60 1000 367.0 367.0 38.0 DS90UH926QSQE/NOPB WQFN NKB 60 250 213.0 191.0 55.0 DS90UH926QSQX/NOPB WQFN NKB 60 2000 367.0 367.0 38.
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MECHANICAL DATA NKB0060B SQA60B (Rev B) www.ti.
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