Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - serialisers FPD-Link, LVDS TQFP 48

DS90UR124Q, DS90UR241Q

www.ti.com

SNLS231N –SEPTEMBER 2006–REVISED MARCH 2013

DS90UR124Q DS90UR241Q 5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and

Deserializer Chipset

Check for Samples: DS90UR124Q, DS90UR241Q

FEATURES

APPLICATIONS

• Supports Displays with 18-bit Color Depth

• Automotive Central Information Display

• 5MHz to 43MHz Pixel Clock • Automotive Instrument Cluster Display

• Automotive Grade Product AEC-Q100 Grade 2 • Automotive Heads-Up Display

Qualified

• Remote Camera-based Driver Assistance

• 24:1 Interface Compression Systems

• Embedded Clock with DC Balancing Supports

DESCRIPTION

AC-coupled Data Transmission

The DS90UR241/124 Chipset translates a 24-bit

• Capable to Drive up to 10 Meters Shielded

parallel bus into a fully transparent data/control FPD-

Twisted-pair Cable

Link II LVDS serial stream with embedded clock

• No Reference Clock Required (Deserializer)

information. This chipset is ideally suited for driving

graphical data to displays requiring 18-bit color depth

• Meets ISO 10605 ESD - Greater than 8 kV HBM

- RGB666 + HS, VS, DE + 3 additional general

ESD Structure

purpose data channels. This single serial stream

• Hot Plug Support

simplifies transferring a 24-bit bus over PCB traces

• EMI Reduction - Serializer Accepts Spread

and cable by eliminating the skew problems between

Spectrum Input; Data randomization and

parallel data and clock paths. It saves system cost by

shuffling on serial link; Deserializer provides

narrowing data paths that in turn reduce PCB layers,

Adjustable PTO (progressive turn-on) LVCMOS cable width, and connector size and pins.

outputs

The DS90UR241/124 incorporates FPD-Link II LVDS

• @Speed BIST (built-in self test) to validate

signaling on the high-speed I/O. FPD-Link II LVDS

LVDS transmission path

provides a low power and low noise environment for

reliably transferring data over a serial transmission

• Individual power-down controls for both

path. By optimizing the Serializer output edge rate for

Transmitter and Receiver

the operating frequency range EMI is further reduced.

• Power supply range 3.3V ± 10%

In addition, the device features pre-emphasis to boost

• 48-pin TQFP package for Transmitter and 64-

signals over longer distances using lossy cables.

pin TQFP package for Receiver

Internal DC balanced encoding/decoding is used to

• Temperature range -40°C to +105°C

support AC-Coupled interconnects. Using TI’s

proprietary random lock, the Serializer’s parallel data

• Backward Compatible Mode with

are randomized to the Deserializer without the need

DS90C241/DS90C124

of REFCLK.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (35 pages)

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DS90UR124Q, DS90UR241Q www.ti.
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DS90UR124Q, DS90UR241Q SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013 www.ti.
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DS90UR124Q, DS90UR241Q www.ti.com SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013 Absolute Maximum Ratings (1) (2) −0.3V to +4V Supply Voltage (VDD) LVCMOS Input Voltage −0.3V to (VDD +0.3V) LVCMOS Output Voltage −0.3V to (VDD +0.3V) LVDS Receiver Input Voltage −0.3V to +3.9V LVDS Driver Output Voltage −0.3V to +3.
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DS90UR124Q, DS90UR241Q SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013 www.ti.com ELECTRICAL CHARACTERISTICS (1) (2) (3) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Pin/Freq. Min Typ Max Unit 2.0 VDD V GND 0.8 V -0.8 -1.5 V LVCMOS DC SPECIFICATIONS VIH High Level Input Voltage VIL Low Level Input Voltage VCL Input Clamp Voltage IIN Input Current Tx: DIN[0:23], TCLK, TPWDNB, DEN, TRFB, RAOFF, VODSEL, RES0.
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DS90UR124Q, DS90UR241Q www.ti.com SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013 ELECTRICAL CHARACTERISTICS(1)(2)(3) (continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Pin/Freq.
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DS90UR124Q, DS90UR241Q SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013 www.ti.com Serializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified.
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DS90UR124Q, DS90UR241Q www.ti.com SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013 Deserializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Pin/Freq.
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DS90UR124Q, DS90UR241Q SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013 www.ti.com AC Timing Diagrams and Test Circuits Device Pin Name Signal Pattern TCLK ODD DIN EVEN DIN Figure 1. Serializer Input Checkerboard Pattern Device Pin Name Signal Pattern RCLK ODD ROUT EVEN ROUT Figure 2. Deserializer Output Checkerboard Pattern DOUT+ 10 pF Vdiff 100: 80% 80% 20% DOUT- 10 pF Vdiff = 0V 20% tLLHT tLHLT Vdiff = (DOUT+) - (DOUT-) Figure 3.
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DS90UR124Q, DS90UR241Q www.ti.com SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013 tTCP TCLK VDD/2 tDIS VDD/2 VDD/2 tDIH VDD DIN [0:23] Setup VDD/2 Hold VDD/2 0V Figure 5.
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DS90UR124Q, DS90UR241Q SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013 www.ti.com 2.0V PWDWN 0.8V tHZD or tLZD TCLK tZHD or tZLD tPLD Output Active TRI-STATE DOUT± TRI-STATE DIN SYMBOL N SYMBOL N+1 SYMBOL N+2 | | Figure 7.
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DS90UR124Q, DS90UR241Q SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013 PARALLEL-TO-SERIAL www.ti.com 24 DIN DOUT+ RL 20194528 DOUT- TCLK VOD = (DOUT+) – (DOUT−) Differential output signal is shown as (DOUT+) – (DOUT−), device in Data Transfer mode. Figure 10. Serializer VOD Diagram 80% 80% Deserializer 20% 4 pF lumped 20% tCLH tCHL Figure 11.
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DS90UR124Q, DS90UR241Q SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013 www.ti.com 500: VREF CL = 8 pF VREF = VDD/2 for tZLR or tLZR, + - VREF = 0V for tZHR or tHZR REN NOTE: CL includes instrumentation and fixture capacitance within 6 cm of ROUT [23:0]. VOH VDD/2 REN VDD/2 VOL tLZR tZLR VOL + 0.5V VOL + 0.5V VOL ROUT [23:0] tHZR tZHR VOH VOH - 0.5V VOH + 0.5V Figure 13. Deserializer TRI-STATE Test Circuit and Timing 2.0V PWDN 0.
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DS90UR124Q, DS90UR241Q www.ti.com SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013 tRCP tRDC RCLK tRDC VDD/2 VDD/2 tROS ROUT [7:0] VDD/2 (group 1) Data Valid Before RCLK tROH Data Valid After RCLK VDD/2 | -2 UI | +2 UI tROS ROUT [15:8] VDD/2 (group 2) Data Valid Before RCLK | -1 UI ROUT [23:16] VDD/2 (group 3) tROS Data Valid Before RCLK tROH Data Valid After RCLK VDD/2 | +1 UI tROH Data Valid After RCLK VDD/2 | +1 UI | -1 UI Figure 15.
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DS90UR124Q, DS90UR241Q SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013 www.ti.com Sampling Window Ideal Data Bit Beginning Ideal Data Bit End RxIN_TOL -L RxIN_TOL -R Ideal Center Position (tBIT/2) tBIT (1 UI) RxIN_TOL_L is the ideal noise margin on the left of the figure, with respect to ideal. RxIN_TOL_R is the ideal noise margin on the right of the figure, with respect to ideal. Figure 17.
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DS90UR124Q, DS90UR241Q www.ti.com SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013 DS90UR241 Serializer Pin Descriptions Pin # Pin Name I/O/PWR Description LVCMOS PARALLEL INTERFACE PINS 4-1, DIN[23:0] 48-44, 41-32, 29-25 LVCMOS_I Transmitter Parallel Interface Data Input Pins. Tie LOW if unused, do not float. 10 LVCMOS_I Transmitter Parallel Interface Clock Input Pin. Strobe edge set by TRFB configuration pin.
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DS90UR124Q, DS90UR241Q SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013 www.ti.
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DS90UR124Q, DS90UR241Q www.ti.com SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013 DS90UR124 Deserializer Pin Descriptions (continued) Pin # Pin Name I/O/PWR Description 63 RAOFF LVCMOS_I Randomizer Control Input Pin (See Table 2 for more details.) RAOFF = H, Backwards compatible mode for use with DS90C241 Serializer. RAOFF = L; Additional randomization ON (Default), Selects 2E7 LSFR setting.
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DS90UR124Q, DS90UR241Q SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013 www.ti.com Functional Description The DS90UR241 Serializer and DS90UR124 Deserializer chipset is an easy-to-use transmitter and receiver pair that sends 24-bits of parallel LVCMOS data over a single serial LVDS link from 120 Mbps to 1.03 Gbps throughput.
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DS90UR124Q, DS90UR241Q www.ti.com SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013 CLK1, CLK0, DCA, DCB are four overhead bits transmitted along the single LVDS serial data stream (Figure 24). The CLK1 bit is always high and the CLK0 bit is always low. The CLK1 and CLK0 bits function as the embedded clock bits in the serial stream. DCB functions as the DC Balance control bit. It does not require any pre-coding of data on transmit side.
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DS90UR124Q, DS90UR241Q SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013 www.ti.com PRE-EMPHASIS The DS90UR241 features a Pre-Emphasis function used to compensate for long or lossy transmission media. Cable drive is enhanced with a user selectable Pre-Emphasis feature that provides additional output current during transitions to counteract cable loading effects. The transmission distance will be limited by the loss characteristics and quality of the media.
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DS90UR124Q, DS90UR241Q www.ti.com SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013 SIGNAL QUALITY ENHANCERS The DS90UR124 Deserializer supports two signal quality enhancers. The SLEW pin is used to increase the drive strength of the LVCMOS outputs when driving heavy loads. SLEW allows output drive strength for high or low current drive. Default setting is LOW for low drive at 2 mA and HIGH for high drive at 4 mA.
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DS90UR124Q, DS90UR241Q SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013 www.ti.com APPLICATION INFORMATION USING THE DS90UR241 AND DS90UR124 The DS90UR241/DS90UR124 Serializer/Deserializer (SERDES) pair sends 24 bits of parallel LVCMOS data over a serial LVDS link up to 1.03 Gbps. Serialization of the input data is accomplished using an on-board PLL at the Serializer which embeds clock with the data.
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DS90UR124Q, DS90UR241Q www.ti.
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DS90UR124Q, DS90UR241Q SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013 www.ti.com TRANSMISSION MEDIA The Serializer and Deserializer are to be used in point-to-point configuration, through a PCB trace, or through twisted pair cable. In a point-to-point configuration, the transmission media needs be terminated at both ends of the transmitter and receiver pair. Interconnect for LVDS typically has a differential impedance of 100 Ohms.
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DS90UR124Q, DS90UR241Q www.ti.com SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013 DS90UR124 (DES) 3.3V 3.3V VDD VDD C1 VDD VDD C5 C6 RIN+ RINC10 RPWDNB BISTM 3.
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DS90UR124Q, DS90UR241Q SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013 www.ti.com A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of these external bypass capacitors, usually in the range of 20-30 MHz range.
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DS90UR124Q, DS90UR241Q www.ti.com SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013 100 nF DOUT+ 100 nF RIN+ 100: DOUT- 100: 100 nF RIN- 100 nF bit23 CLK0 bit21 bit22 bit20 bit19 bit17 bit18 bit16 bit15 bit14 bit12 bit13 DCB bit11 DCA bit9 bit10 bit8 bit7 bit6 bit4 bit5 bit3 bit1 bit2 bit0 CLK1 Figure 23. AC Coupled Application 1 CLK cycle *Note: bits [0-23] are not physically located in positions shown above since bits [0-23] are scrambled and DC Balanced Figure 24.
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DS90UR124Q, DS90UR241Q SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013 www.ti.com Truth Tables Table 1. DS90UR241 Serializer Truth Table TPWDNB (Pin 9) DEN (Pin 18) RAOFF (Pin 12) Tx PLL Status (Internal) LVDS Outputs (Pins 19 and 20) L X X X Hi Z H L X X Hi Z H H X Not Locked Hi Z H H L Locked Serialized Data with Embedded Clock (DS90UR124 compatible) H H H Locked Serialized Data with Embedded Clock (DS90C124 compatible) Table 2.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com (4) 24-Nov-2013 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DS90UR124IVSX/NOPB TQFP PAG 64 1000 330.0 24.4 13.0 13.0 1.45 16.0 24.0 Q2 DS90UR124QVSX/NOPB TQFP PAG 64 1000 330.0 24.4 13.0 13.0 1.45 16.0 24.0 Q2 DS90UR241IVSX/NOPB TQFP PFB 48 1000 330.0 16.4 9.3 9.3 2.2 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS90UR124IVSX/NOPB TQFP PAG 64 1000 367.0 367.0 45.0 DS90UR124QVSX/NOPB TQFP PAG 64 1000 367.0 367.0 45.0 DS90UR241IVSX/NOPB TQFP PFB 48 1000 367.0 367.0 38.0 DS90UR241QVSX/NOPB TQFP PFB 48 1000 367.0 367.0 38.
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MECHANICAL DATA MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996 PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 48 0,08 M 33 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 1,05 0,95 0°– 7° 0,75 0,45 Seating Plane 0,08 1,20 MAX 4040282 / C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°– 7° 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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