Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - serialisers FPD-Link II, LVDS WQFN 48

DS90UR905Q, DS90UR906Q

www.ti.com

SNLS313G –SEPTEMBER 2009–REVISED APRIL 2013

DS90UR905Q/DS90UR906Q 5 - 65 MHz 24-bit Color FPD-Link II Serializer and Deserializer

Check for Samples: DS90UR905Q, DS90UR906Q

FEATURES

DESCRIPTION

The DS90UR905Q/906Q chipset translates a parallel

• 5 – 65 MHz PCLK Support (140 Mbps – 1.82

RGB Video Interface into a high-speed serialized

Gbps)

interface over a single pair. This serial bus scheme

• AC Coupled STP Interconnect Cable up to 10

greatly eases system design by eliminating skew

Meters

problems between clock and data, reduces the

number of connector pins, reduces the interconnect

• Integrated Terminations on Ser and Des

size, weight, and cost, and overall eases PCB layout.

• @ Speed Link BIST Mode and Reporting Pin

In addition, internal DC balanced decoding is used to

• Optional I2C Compatible Serial Control Bus

support AC-coupled interconnects.

• RGB888 + VS, HS, DE Support

The DS90UR905Q Ser (serializer) embeds the clock,

• Power Down Mode Minimizes Power

balances the data payload, and level shifts the

Dissipation

signals to high-speed low voltage differential

signaling. Up to 24 inputs are serialized along with

• 1.8V or 3.3V Compatible LVCMOS I/O Interface

the three video control signals. This supports full 24-

• Automotive Grade Product: AEC-Q100 Grade 2

bit color or 18-bit color and 6 general purpose signals

Qualified

(e.g. Audio I2S) applications.

• >8 kV HBM and ISO 10605 ESD Rating

The DS90UR906Q Des (deserializer) recovers the

• Backward Compatible Mode for Operation with

data (RGB) and control signals and extracts the clock

Older Generation Devices

from the serial stream. It is able to lock to the

incoming data stream without the use of a training

SERIALIZER — DS90UR905Q

sequence or special SYNC patterns, and does not

• RGB888 + VS/HS/DE Serialized to 1 Pair FPD-

require a reference clock. A link status (LOCK) output

Link II

signal is provided.

• Randomizer/Scrambler — DC-Balanced Data

Serial transmission is optimized by a user selectable

Stream

de-emphasis, differential output level select features,

• Selectable Output VOD and Adjustable De-

and receiver equalization. EMI is minimized by the

Emphasis

use of low voltage differential signaling, receiver drive

DESERIALIZER — DS90UR906Q

strength control, and spread spectrum clocking

compatibility. The Des may be configured to generate

• FAST Random Data Lock; No Reference Clock

Spread Spectrum Clock and Data on its parallel

Required

outputs.

• Adjustable Input Receiver Equalization

The DS90UR905Q (Ser) is offered in a 48-pin WQFN

• LOCK (Real Time Link Status) Reporting Pin

and the DS90UR906Q (Des) is offered in a 60-pin

• EMI Minimization on Output Parallel Bus

WQFN package. They are specified over the

(SSCG)

automotive AEC-Q100 grade 2 temperature range of

-40°C to +105°C.

• Output Slew Control (OS)

APPLICATIONS

• Automotive Display for Navigation

• Automotive Display for Entertainment

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (54 pages)

PAGE 1
DS90UR905Q, DS90UR906Q www.ti.com SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 DS90UR905Q/DS90UR906Q 5 - 65 MHz 24-bit Color FPD-Link II Serializer and Deserializer Check for Samples: DS90UR905Q, DS90UR906Q FEATURES DESCRIPTION • The DS90UR905Q/906Q chipset translates a parallel RGB Video Interface into a high-speed serialized interface over a single pair.
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DS90UR905Q, DS90UR906Q SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 www.ti.com Applications Diagram HOST Graphics Processor RGB Digital Display Interface VDDIO VDDn (1.8V or 3.3V) 1.8V R[7:0] G[7:0] B[7:0] HS VS DE PCLK PDB VDDn VDDIO 1.8V (1.8V or 3.
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DS90UR905Q, DS90UR906Q www.ti.
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DS90UR905Q, DS90UR906Q SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 www.ti.
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DS90UR905Q, DS90UR906Q www.ti.com SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 DS90UR905Q Serializer Pin Functions(1) (continued) Pin Name Pin # I/O, Type DE 5 I, LVCMOS w/ pull-down Description Data Enable Input Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the Control Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00).
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DS90UR905Q, DS90UR906Q SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 www.ti.com DS90UR905Q Serializer Pin Functions(1) (continued) Pin Name Pin # I/O, Type Description FPD-Link II Serial Interface DOUT+ 20 O, LVDS True Output. The output must be AC Coupled with a 100 nF capacitor. DOUT- 19 O, LVDS Inverting Output. The output must be AC Coupled with a 100 nF capacitor. VDDL 7 Power Logic Power, 1.8 V ±5% VDDP 14 Power PLL Power, 1.
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DS90UR905Q, DS90UR906Q www.ti.
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DS90UR905Q, DS90UR906Q SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 www.ti.com DS90UR906Q Deserializer Pin Functions (1) Pin Name Pin # I/O, Type Description LVCMOS Parallel Interface R[7:0] 33, 34, 35, 36, 37, 39, 40, 41 I, STRAP, O, LVCMOS RED Parallel Interface Data Output Pins (MSB = 7, LSB = 0) In power-down (PDB = 0), outputs are controlled by the OSS_SEL (See Table 8). These pins are inputs during power-up (See STRAP Inputs).
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DS90UR905Q, DS90UR906Q www.ti.
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DS90UR905Q, DS90UR906Q SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 www.ti.com DS90UR906Q Deserializer Pin Functions(1) (continued) Pin Name Pin # I/O, Type Description FPD-Link II Serial Interface RIN+ 49 I, LVDS True Input. The input must be AC Coupled with a 100 nF capacitor. RIN- 50 I, LVDS Inverting Input. The input must be AC Coupled with a 100 nF capacitor.
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DS90UR905Q, DS90UR906Q www.ti.com SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) (3) −0.3V to +2.5V Supply Voltage – VDDn (1.8V) −0.3V to +4.0V Supply Voltage – VDDIO −0.3V to +(VDDIO + 0.3V) LVCMOS I/O Voltage Receiver Input Voltage −0.3V to (VDD + 0.
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DS90UR905Q, DS90UR906Q SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 www.ti.com Recommended Operating Conditions Min Nom Max Supply Voltage (VDDn) 1.71 1.8 1.89 LVCMOS Supply Voltage (VDDIO) 1.71 1.8 1.89 OR LVCMOS Supply Voltage (VDDIO) 3.0 3.3 3.6 Operating Free Air Temperature (TA) −40 +25 +105 °C 65 MHz 50 mVP-P PCLK Clock Frequency 5 Supply Noise (1) (1) Units V Supply noise testing was done with minimum capacitors on the PCB.
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DS90UR905Q, DS90UR906Q www.ti.com SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 Serializer DC Electrical Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3) Symbol Parameter Conditions Pin/Freq Min Typ Max 75 85 Units SUPPLY CURRENT IDDT1 IDDIOT1 IDDT2 Serializer Supply Current (includes load current) RL = 100Ω, f = 65MHz Checker Board Pattern, De-emph = 3KΩ VODSEL = H, Figure 9 IDDIOZ All VDD pins VDDIO= 1.
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DS90UR905Q, DS90UR906Q SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 www.ti.com Deserializer DC Electrical Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Pin/Freq.
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DS90UR905Q, DS90UR906Q www.ti.com SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 Serializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified.
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DS90UR905Q, DS90UR906Q SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 www.ti.com Deserializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Pin/Freq. Min Typ Max Units tRCP PCLK Output Period tRCP = tTCP PCLK 15.
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DS90UR905Q, DS90UR906Q www.ti.com SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 Recommended Timing for the Serial Control Bus Over 3.3V supply and temperature ranges unless otherwise specified. Symbol fSCL Parameter SCL Clock Frequency Conditions Min Typ Max Units Standard Mode >0 100 kHz Fast Mode >0 400 kHz Standard Mode 4.7 us Fast Mode 1.3 us Standard Mode 4.0 us Fast Mode 0.6 us Hold time for a start or a repeated start condition, Figure 18 Standard Mode 4.
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DS90UR905Q, DS90UR906Q SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 www.ti.com AC Timing Diagrams and Test Circuits A A' CA Scope 50: 50: CB B B' 50: 50: Single-Ended Figure 1. Serializer Test Circuit DOUT+ VOD- VOD+ DOUT- VOS Differential GND VOD+ (DOUT+) - (DOUT+) 0V VODp-p VOD- Figure 2. Serializer Output Waveforms +VOD 80% (DOUT+) - (DOUT-) 0V 20% -VOD tLLHT tLHLT Figure 3.
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DS90UR905Q, DS90UR906Q www.ti.com SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 PDB PCLK 1/2 VDDIO "X" active tPLD DOUT (Diff.) Driver On Driver OFF, VOD = 0V Figure 5. Serializer Lock Time 1/2 VDDIO PDB PCLK active "X" tXZD DOUT (Diff.) active Driver OFF, VOD = 0V Figure 6. Serializer Disable Time RGB[7:0], HS, VS, DE SYMBOL N SYMBOL N+1 tSD PCLK (RFB = L) START BIT DOUT 0 (Diff.) STOP START BIT BIT 1 2 27 SYMBOL N-1 0 STOP BIT 1 2 27 SYMBOL N Figure 7.
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DS90UR905Q, DS90UR906Q SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 www.ti.com tDJIT tDJIT VOD (+) DOUT (Diff.) TxOUT_E_O 0V VOD (-) tBIT (1 UI) Figure 8. Serializer Output Jitter VDDIO PCLK w/ RFB = L GND VDDIO RGB[n] (odd), VS, HS GND VDDIO RGB[n] (even), DE GND Figure 9. Checkerboard Data Pattern VDDIO 80% 20% GND tCLH tCHL Figure 10. Deserializer LVCMOS Transition Times START BIT STOP START BIT BIT STOP BIT RIN (Diff.
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DS90UR905Q, DS90UR906Q www.ti.com SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 1/2 VDDIO PDB RIN (Diff.) active "X" tXZR PCLK, RGB[7:0], DE, HS, VS, PASS, LOCK active Z (TRI-STATE) Figure 12. Deserializer Disable Time (OSS_SEL = 0) PDB 2.0V 0.8V RIN (Diff.) 'RQ¶W &DUH tDDLT LOCK TRI-STATE or LOW Z or L tRxZ RGB[7:0], HS, VS, DE TRI-STATE or LOW or Pulled Up PCLK (RFB = L) Z or L or PU TRI-STATE or LOW OFF IN LOCK TIME Z or L ACTIVE OFF Figure 13.
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DS90UR905Q, DS90UR906Q SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 www.ti.com VDDIO PCLK w/ RFB = H 1/2 VDDIO GND RGB[n], VS, HS, DE 1/2 VDDIO VDDIO 1/2 VDDIO tROS GND tROH Figure 15. Deserializer Output Data Valid (Setup and Hold) Times with SSCG = On Ideal Data Bit End Sampling Window Ideal Data Bit Beginning RxIN_TOL Left VTH 0V VTL RxIN_TOL Right Ideal Center Position (tBIT/2) tBIT (1 UI) tRJIT = RxIN_TOL (Left + Right) - tRJIT Sampling Window = 1 UI Figure 16.
PAGE 23
DS90UR905Q, DS90UR906Q www.ti.com SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 Functional Description The DS90UR905Q / DS90UR906Q chipset transmits and receives 27-bits of data (24-high speed color bits and 3 low speed video control signals) over a single serial FPD-Link II pair operating at 140Mbps to 1.82Gbps. The serial stream also contains an embedded clock, video control signals and the DC-balance information which enhances signal quality and supports AC coupling.
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DS90UR905Q, DS90UR906Q SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 www.ti.com Table 2.
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DS90UR905Q, DS90UR906Q www.ti.com SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 EMI Reduction Features Ser — Spread Spectrum Compatibility The Ser PCLK is capable of tracking spread spectrum clocking (SSC) from a host source. The PCLK will accept spread spectrum tracking up to 35kHz modulation and ±0.5, ±1 or ±2% deviations (center spread). The maximum conditions for the PCLK input are: a modulation frequency of 35kHz and amplitude deviations of ±2% (4% total).
PAGE 26
DS90UR905Q, DS90UR906Q SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 www.ti.com Power Saving Features Ser — Power Down Feature (PDB) The Ser has a PDB input pin to ENABLE or POWER DOWN the device. This pin is controlled by the host and is used to save power, disabling the link when the display is not needed. In the POWER DOWN mode, the highspeed driver outputs are both pulled to VDD and present a 0V VOD state. Note – in POWER DOWN, the optional Serial Bus Control Registers are RESET.
PAGE 27
DS90UR905Q, DS90UR906Q www.ti.com SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 Table 5. Receiver Equalization Configuration Table (continued) INPUTS EQ3 EQ2 EQ1 EQ0 Effect L H H H ~6 dB H L L H ~7.5 dB H L H H ~9 dB H H L H ~10.5 dB H H H H ~12 dB X X X L OFF* * Default Setting is EQ = Off EMI Reduction Features Des — Output Slew (OS_PCLK/DATA) The parallel bus outputs (RGB[7:0], VS, HS, DE and PCLK) of the Des feature a selectable output slew.
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DS90UR905Q, DS90UR906Q SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 www.ti.com Table 7. SSCG Configuration (LF_MODE = H) — Des Output SSC[3:0] Inputs LH_MODE = H (5 - 20 MHz) Result SSC3 SSC2 SSC1 SSC0 fdev (%) fmod (kHz) L L L L L L L Off Off H ±0.5 L L H L ±1.0 L L H H ±1.5 L H L L ±2.0 L H L H ±0.5 L H H L ±1.0 L H H H ±1.5 H L L L ±2.0 H L L H ±0.5 H L H L ±1.0 H L H H ±1.5 H H L L ±2.0 H H L H ±0.5 H H H L ±1.
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DS90UR905Q, DS90UR906Q www.ti.com SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 Des — CLOCK-DATA RECOVERY STATUS FLAG (LOCK) and OUTPUT STATE SELECT (OSS_SEL) When PDB is driven HIGH, the CDR PLL begins locking to the serial input and LOCK goes from TRI-STATE to LOW (depending on the value of the OSS_SEL setting).
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DS90UR905Q, DS90UR906Q SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 www.ti.com PDB (DES) RIN (Diff.) active serial stream X H LOCK Z H L L Z RGB[7:0], HS, VS, DE L L L PCLK* (DES) L L L PASS H H L Z L Locking OFF Active Z C0 or C1 Error In Bit Stream (Loss of LOCK) Active OFF CONDITIONS: * RFB = L, and OSS_SEL = L Figure 23. Des Outputs with Output State Select Low (OSS_SEL = L) PDB (DES) RIN (Diff.
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DS90UR905Q, DS90UR906Q www.ti.com SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 Table 10. OSC_SEL (Oscillator) Configuration OSC_SEL[2:0] INPUTS PCLK Oscillator Output OSC_SEL2 OSC_SEL1 OSC_SEL0 L L L Off – Feature Disabled – Default L L H 50 MHz ±40% L H L 25 MHz ±40% L H H 16.7 MHz ±40% H L L 12.5 MHz ±40% H L H 10 MHz ±40% H H L 8.3 MHz ±40% H H H 6.3 MHz ±40% PDB (DES) RIN (Diff.
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DS90UR905Q, DS90UR906Q SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 PDB www.ti.com 2.0V LOCK OP_ LOW SET (Strap pin) User controlled User controlled OP_ LOW RELEASE/SET (Register) RGB[7:0], HS, VS, DE TRISTATE ACTIVE ACTIVE PCLK TRISTATE ACTIVE ACTIVE Figure 26. OP_LOW Auto Set PDB 2.0V LOCK OP_LOW SET (Strap pin) User controlled User controlled OP_ LOW RELEASE/SET (Register) RGB[7:0], HS, VS, DE TRISTATE ACTIVE PCLK TRISTATE ACTIVE Figure 27.
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DS90UR905Q, DS90UR906Q www.ti.com SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 Des — Control Signal Filter — Optional The Des provides an optional Control Signal (VS, HS, DE) filter that monitors the three video control signals and eliminates any pulses that are 1 or 2 PCLKs wide. Control signals must be 3 pixel clocks wide (in its HIGH or LOW state, regardless of which state is active). This is set by the CONFIG[1:0] or by the Control Register.
PAGE 34
DS90UR905Q, DS90UR906Q SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 www.ti.com Step 1: Place the DS90UR905Q Ser in BIST Mode by setting Ser BISTEN = H. For the DS90UR905Q Ser or DS99R421 FPD-Link II Ser BIST Mode is enabled via the BISTEN pin. For the DS90C241 Ser or DS90UR241 Ser, BIST mode is enetered by setting all the input data of the device to Low state. A PCLK is required for all the Ser options.
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DS90UR905Q, DS90UR906Q www.ti.com SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 SER BISTEN (SER) DES Outputs BISTEN (DES) Case 1 - Pass PCLK (RFB = L) RGB[7:0] HS, VS, DE DATA (internal) PASS Prior Result PASS PASS X X X FAIL Prior Result Normal Case 2 - Fail X = bit error(s) DATA (internal) PRBS BIST Result Held BIST Test BIST Duration Normal Figure 29.
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DS90UR905Q, DS90UR906Q SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 www.ti.com SDA SCL S P START condition, or START repeat condition STOP condition Figure 31. START and STOP Conditions To communicate with a remote device, the host controller (master) sends the slave address and listens for a response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low.
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DS90UR905Q, DS90UR906Q www.ti.com SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 Register Address Slave Address A 2 S A 1 A 0 0 Data a c k a c k a c k P Figure 33. Serial Control Bus — WRITE Table 14.
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DS90UR905Q, DS90UR906Q SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 www.ti.com Table 15.
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DS90UR905Q, DS90UR906Q www.ti.com SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 Table 15. DESERIALIZER — Serial Bus Control Registers (continued) ADD ADD Register Name (dec) (hex) 3 4 3 4 Des Features 2 CMLOUT Config Bit(s) R/W Defau Function lt (bin) 7:5 R/W 000 4 R/W 0 3:0 R/W 0000 7 R/W 0 6:0 R/W Description EQ Gain 000: 001: 010: 011: 100: 101: 110: 111: EQ Enable 0: EQ = disabled 1: EQ = enabled SSC IF LF_MODE = 0, then: 000: SSCG OFF 0001: fdev = ±0.
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DS90UR905Q, DS90UR906Q SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 www.ti.com APPLICATIONS INFORMATION DISPLAY APPLICATION The DS90UR905Q/906Q chipset is intended for interface between a host (graphics processor) and a Display. It supports an 24-bit color depth (RGB888) and up to 1024 X 768 display formats. In a RGB888 application, 24 color bits (R[7:0], G[7:0], B[7:0]), Pixel Clock (PCLK) and three control bits (VS, HS and DE) are supported across the serial link with PCLK rates from 5 to 65 MHz.
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DS90UR905Q, DS90UR906Q www.ti.com SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 DS90UR905Q (SER) VDDIO VDDIO C9 C7 FB1 C3 R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 LVCMOS Parallel Video Interface VDDTX VDDHS HS VS DE LVCMOS Control Interface BISTEN PDB C12 CONFIG1 CONFIG1 RFB C4 FB2 C5 FB3 C6 FB4 C8 C10 VDDP C11 VDDL C1 Serial FPD-Link II Interface DOUT+ DOUTC2 B7 B6 B5 B4 B3 B2 B1 B0 PCLK 1.8V VDDIO VODSEL De-Emph 1.
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DS90UR905Q, DS90UR906Q SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 www.ti.com DS90UR906Q (DES) 1.8V VDDL C14 C11 FB1 C3 FB3 C4 FB4 C5 VDDIO VDDIO C8 VDDSC FB2 C12 C15 VDDIO C9 VDDPR VDDIO C10 VDDR FB5 C16 C6 VDDIR VDDIO EXAMPLE: STRAP Input Pull-Ups (10k) VDDCMLO FB6 C17 C7 C1 Serial FPD-Link II Interface RIN+ RINCMF C2 C13 TP_A CMLOUTP CMLOUTN TP_B Host Control BISTEN PDB C18 1.8V 10k ID[X] SCL SDA RID C1 - C2 = 0.1 PF (50 WV) C3 - C12 = 0.1 PF C13 - C17 = 4.
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DS90UR905Q, DS90UR906Q www.ti.com SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 TRANSMISSION MEDIA The Ser/Des chipset is intended to be used in a point-to-point configuration, through a PCB trace, or through twisted pair cable. The Ser and Des provide internal terminations providing a clean signaling environment. The interconnect for LVDS should present a differential impedance of 100 Ohms. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities.
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DS90UR905Q, DS90UR906Q SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 www.ti.com – 3S = space to LVCMOS signal Minimize the number of Vias Use differential connectors when operating above 500Mbps line speed Maintain balance of the traces Minimize skew within the pair Terminate as close to the TX outputs and RX inputs as possible • • • • • Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the TI web site at: www.ti.
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DS90UR905Q, DS90UR906Q www.ti.
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DS90UR905Q, DS90UR906Q SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 • • • 46 www.ti.com Updated figures 14 and 15 to reflect data measurement at VDDIO/2 Updated fig 35 — C13 changed to 4.
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DS90UR905Q, DS90UR906Q www.ti.com SNLS313G – SEPTEMBER 2009 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision F (April 2013) to Revision G • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 16-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device DS90UR905QSQ/NOPB Package Package Pins Type Drawing WQFN RHS 48 DS90UR905QSQE/NOPB WQFN RHS DS90UR905QSQX/NOPB WQFN RHS WQFN SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 48 2500 330.0 16.4 7.3 7.3 1.3 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS90UR905QSQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 DS90UR905QSQE/NOPB WQFN RHS 48 250 213.0 191.0 55.0 DS90UR905QSQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 DS90UR906QSQ/NOPB WQFN NKB 60 1000 367.0 367.0 38.0 DS90UR906QSQE/NOPB WQFN NKB 60 250 213.0 191.0 55.
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MECHANICAL DATA NKB0060B SQA60B (Rev B) www.ti.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.