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DS92LV010A

www.ti.com

SNLS007E –MAY 1998–REVISED APRIL 2013

DS92LV010A Bus LVDS 3.3/5.0V Single Transceiver

Check for Samples: DS92LV010A

FEATURES

DESCRIPTION

The DS92LV010A is one in a series of transceivers

• Bus LVDS Signaling (BLVDS)

designed specifically for the high speed, low power

• Designed for Double Termination Applications

proprietary bus backplane interfaces. The device

• Balanced Output Impedance

operates from a single 3.3V or 5.0V power supply

and includes one differential line driver and one

• Lite Bus Loading 5pF Typical

receiver. To minimize bus loading the driver outputs

• Glitch Free Power Up/Down (Driver Disabled)

and receiver inputs are internally connected. The

• 3.3V or 5.0V Operation

logic interface provides maximum flexibility as 4

separate lines are provided (DIN, DE, RE, and

• ±1V Common Mode Range

ROUT). The device also features flow through which

• ±100mV Receiver Sensitivity

allows easy PCB routing for short stubs between the

• High Signaling Rate Capability (Above 100

bus pins and the connector. The driver has 10 mA

Mbps)

drive capability, allowing it to drive heavily loaded

backplanes, with impedance as low as 27 Ohms.

• Low Power CMOS Design

• Product Offered in 8 Lead SOIC Package

The driver translates between TTL levels (single-

ended) to Low Voltage Differential Signaling levels.

• Industrial Temperature Range Operation

This allows for high speed operation, while

consuming minimal power with reduced EMI. In

addition the differential signaling provides common

mode noise rejection of ±1V.

The receiver threshold is ±100mV over a ±1V

common mode range and translates the low voltage

differential levels to standard (CMOS/TTL) levels.

CONNECTION DIAGRAM

Figure 1. SOIC Package

See Package Number D0008A

BLOCK DIAGRAM

Figure 2.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (17 pages)

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DS92LV010A www.ti.com SNLS007E – MAY 1998 – REVISED APRIL 2013 DS92LV010A Bus LVDS 3.3/5.0V Single Transceiver Check for Samples: DS92LV010A FEATURES DESCRIPTION • • • • • • • • • The DS92LV010A is one in a series of transceivers designed specifically for the high speed, low power proprietary bus backplane interfaces. The device operates from a single 3.3V or 5.0V power supply and includes one differential line driver and one receiver.
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DS92LV010A SNLS007E – MAY 1998 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) (3) Supply Voltage (VCC) 6.0V Enable Input Voltage (DE, RE) −0.3V to (VCC + 0.3V) Driver Input Voltage (DIN) −0.3V to (VCC + 0.3V) Receiver Output Voltage −0.3V to (VCC + 0.3V) (ROUT) −0.
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DS92LV010A www.ti.com SNLS007E – MAY 1998 – REVISED APRIL 2013 (1) (2) 3.3V DC ELECTRICAL CHARACTERISTICS TA = −40°C to +85°C unless otherwise noted, VCC = 3.3V ± 0.3V Parameter Test Conditions VOD Output Differential Voltage ΔVOD VOD Magnitude Change RL = 27Ω, See Figure 3 VOS Offset Voltage ΔVOS Offset Magnitude Change IOSD Output Short Circuit Current VO = 0V, DE = VCC VOH Voltage Output High VID = +100 mV Pin DO+/RI+, DO−/RI− Min Typ Max Units 140 250 360 mV 3 30 mV 1.
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DS92LV010A SNLS007E – MAY 1998 – REVISED APRIL 2013 www.ti.com 5V DC ELECTRICAL CHARACTERISTICS (1) (2) TA = −40°C to +85°C unless otherwise noted, VCC = 5.0V ± 0.5V Parameter Test Conditions VOD Output Differential Voltage ΔVOD VOD Magnitude Change VOS Offset Voltage ΔVOS Offset Magnitude Change IOSD Output Short Circuit Current VO = 0V, DE = VCC VOH Voltage Output High VID = +100 mV Pin RL = 27Ω, See Figure 3 DO+/RI+, DO−/RI− Min Typ Max Units 145 270 390 mV 3 30 mV 1.
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DS92LV010A www.ti.com SNLS007E – MAY 1998 – REVISED APRIL 2013 3.3V AC ELECTRICAL CHARACTERISTICS (1) TA = −40°C to +85°C, VCC = 3.3V ± 0.3V Parameter Test Conditions Min Typ Max Units 1.0 3.0 5.0 ns 1.0 2.8 5.0 ns DIFFERENTIAL DRIVER TIMING REQUIREMENTS tPHLD Differential Prop. Delay High to Low RL = 27Ω, See Figure 4 and Figure 5 CL = 10 pF tPLHD Differential Prop. Delay Low to High tSKD Differential SKEW |t PHLD tPLHD| 0.2 1.0 ns tTLH Transition Time Low to High 0.3 2.
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DS92LV010A SNLS007E – MAY 1998 – REVISED APRIL 2013 www.ti.com 5V AC ELECTRICAL CHARACTERISTICS (1) TA = −40°C to +85°C, VCC = 5.0V ± 0.5V Parameter Test Conditions Min Typ Max Units 0.5 2.7 4.5 ns 0.5 2.5 4.5 ns DIFFERENTIAL DRIVER TIMING REQUIREMENTS tPHLD Differential Prop. Delay High to Low RL = 27Ω, See Figure 4 and Figure 5 CL = 10 pF tPLHD Differential Prop. Delay Low to High tSKD Differential SKEW |t PHLD tPLHD| 0.2 1.0 ns tTLH Transition Time Low to High 0.3 2.
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DS92LV010A www.ti.com SNLS007E – MAY 1998 – REVISED APRIL 2013 Figure 4. Differential Driver Propagation Delay and Transition Time Test Circuit 3V 1.5V DIN 1.5V 0V tPHLD tPLHD DO0V DO+, DO- Differential 0V DO+ (DO+) - (DO-) 80% 80% 0V 20% 20% tTLH tTHL VDIFF = (DO+) - (DO-) Figure 5. Differential Driver Propagation Delay and Transition Time Waveforms Figure 6. Driver TRI-STATE Delay Test Circuit Figure 7.
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DS92LV010A SNLS007E – MAY 1998 – REVISED APRIL 2013 www.ti.com Figure 8. Receiver Propagation Delay and Transition Time Test Circuit Figure 9. Receiver Propagation Delay and Transition Time Waveforms Figure 10. Receiver TRI-STATE Delay Test Circuit Figure 11. Receiver TRI-STATE Delay Waveforms TRI-STATE Delay Waveforms TYPICAL BUS APPLICATION CONFIGURATIONS Figure 12.
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DS92LV010A www.ti.com SNLS007E – MAY 1998 – REVISED APRIL 2013 Figure 13.
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DS92LV010A SNLS007E – MAY 1998 – REVISED APRIL 2013 www.ti.com APPLICATION INFORMATION There are a few common practices which should be implied when designing PCB for BLVDS signaling. Recommended practices are: • Use at least 4 layer PCB board (BLVDS signals, ground, power and TTL signals). • Keep drivers and receivers as close to the (BLVDS port side) connector as possible. • Bypass each BLVDS device and also use distributed bulk capacitance.
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DS92LV010A www.ti.com SNLS007E – MAY 1998 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision D (April 2013) to Revision E • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DS92LV010ATMX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 DS92LV010ATMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS92LV010ATMX SOIC D 8 2500 367.0 367.0 35.0 DS92LV010ATMX/NOPB SOIC D 8 2500 367.0 367.0 35.
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