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DS92LV1021A

www.ti.com

SNLS151G –OCTOBER 2002–REVISED APRIL 2013

DS92LV1021A 16-40 MHz 10 Bit Bus LVDS Serializer

Check for Samples: DS92LV1021A

FEATURES

DESCRIPTION

The DS92LV1021A transforms a 10-bit wide parallel

• Specified Transition Every Data Transfer Cycle

LVCMOS/LVTTL data bus into a single high speed

• Single Differential Pair Eliminates Multi-

Bus LVDS serial data stream with embedded clock.

Channel Skew

The DS92LV1021A can transmit data over

• Flow-Through Pinout for Easy PCB Layout

backplanes or cable. The single differential pair data

path makes PCB design easier. In addition, the

• 400 Mbps Serial Bus LVDS Bandwidth (at 40

reduced cable, PCB trace count, and connector size

MHz Clock)

tremendously reduce cost. Since one output transmits

• 10-bit Parallel Interface for 1 Byte Data Plus 2

both clock and data bits serially, it eliminates clock-to-

Control Bits

data and data-to-data skew. The powerdown pin

saves power by reducing supply current when the

• Programmable Edge Trigger on Clock

device is not being used. Upon power up of the

• Bus LVDS Serial Output Rated for 27Ω Load

Serializer, you can choose to activate synchronization

• Small 28-Lead SSOP Package-DB

mode or use one of TI’s Deserializers in the

synchronization-to-random-data feature. By using the

synchronization mode, the Deserializer will establish

lock to a signal within specified lock times. In

addition, the embedded clock specifies a transition on

the bus every 12-bit cycle. This eliminates

transmission errors due to charged cable conditions.

Furthermore, you may put the DS92LV1021A output

pins into TRI-STATE to achieve a high impedance

state. The PLL can lock to frequencies between 16

MHz and 40 MHz.

Block Diagram

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (18 pages)

PAGE 1
DS92LV1021A www.ti.com SNLS151G – OCTOBER 2002 – REVISED APRIL 2013 DS92LV1021A 16-40 MHz 10 Bit Bus LVDS Serializer Check for Samples: DS92LV1021A FEATURES DESCRIPTION • • The DS92LV1021A transforms a 10-bit wide parallel LVCMOS/LVTTL data bus into a single high speed Bus LVDS serial data stream with embedded clock. The DS92LV1021A can transmit data over backplanes or cable. The single differential pair data path makes PCB design easier.
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DS92LV1021A SNLS151G – OCTOBER 2002 – REVISED APRIL 2013 www.ti.com Functional Description The DS92LV1021A is an upgrade to the DS92LV1021. The DS92LV1021A no longer has a power-up sequence requirement. Like the DS92LV1021, the DS92LV1021A is a 10-bit Serializer designed to transmit data over a differential backplane at clock speeds from 16 to 40MHz. It may also be used to drive data over Unshielded Twisted Pair (UTP) cable.
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DS92LV1021A www.ti.com SNLS151G – OCTOBER 2002 – REVISED APRIL 2013 Ideal Crossing Point The ideal crossing point is the best case start and stop point for a normalized bit. Each ideal crossing point is found by dividing the clock period by twelve--two clock bits plus ten data bits. For example, a 40 MHz clock has a period of 25ns. The 25ns divided by 12 bits is approximately 2.08ns. This means that each bit width is approximately 2.08ns, and the ideal crossing points occur every 2.08ns.
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DS92LV1021A SNLS151G – OCTOBER 2002 – REVISED APRIL 2013 www.ti.com Recommended Operating Conditions Min Nom Max Supply Voltage (VCC) 3.0 3.3 3.6 V Operating Free Air Temperature (TA) −40 +25 +85 °C 100 mVP-P Supply Noise Voltage (VCC) Units Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified.
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DS92LV1021A www.ti.com SNLS151G – OCTOBER 2002 – REVISED APRIL 2013 Serializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified.
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DS92LV1021A SNLS151G – OCTOBER 2002 – REVISED APRIL 2013 www.ti.com Figure 3. Serializer Input Clock Transition Time Timing shown for TCLK_R/F = LOW Figure 4. Serializer Setup/Hold Times Figure 5.
PAGE 7
DS92LV1021A www.ti.com SNLS151G – OCTOBER 2002 – REVISED APRIL 2013 Figure 6. Serializer PLL Lock Time, and PWRDN TRI-STATE Delays Figure 7. SYNC Timing Delays Figure 8.
PAGE 8
DS92LV1021A SNLS151G – OCTOBER 2002 – REVISED APRIL 2013 www.ti.com For an explanation of the Ideal Crossing Point, please see the Application Information Section. Figure 9.
PAGE 9
DS92LV1021A www.ti.com SNLS151G – OCTOBER 2002 – REVISED APRIL 2013 APPLICATION INFORMATION DIFFERENCES BETWEEN THE DS92LV1021A AND THE DS92LV1021 The DS92LV1021A is an enhanced version of the DS92LV1021.
PAGE 10
DS92LV1021A SNLS151G – OCTOBER 2002 – REVISED APRIL 2013 www.ti.com PCB CONSIDERATIONS The Bus LVDS devices Serializer and Deserializer should be placed as close to the edge connector as possible. In multiple Deserializer applications, the distance from the Deserializer to the slot connector appears as a stub to the Serializer driving the backplane traces. Longer stubs lower the impedance of the bus increasing the load on the Serializer and lowers threshold margin at the Deserializers.
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DS92LV1021A www.ti.com SNLS151G – OCTOBER 2002 – REVISED APRIL 2013 Serializer Pin Description Pin Name I/O No. Description DIN I 3–12 Data Input. TTL levels inputs. Data on these pins are loaded into a 10-bit input register. TCLK_R/F I 13 Transmit Clock Rising/Falling strobe select. TTL level input. Selects TCLK active edge for strobing of DIN data. High selects rising edge. Low selects falling edge. DO+ O 22 + Serial Data Output. Non-inverting Bus LVDS differential output.
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DS92LV1021A SNLS151G – OCTOBER 2002 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision F (April 2013) to Revision G • 12 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device DS92LV1021AMSAX DS92LV1021AMSAX/NOP B Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SSOP DB 28 2000 330.0 16.4 8.4 10.7 2.4 12.0 16.0 Q1 SSOP DB 28 2000 330.0 16.4 8.4 10.7 2.4 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS92LV1021AMSAX SSOP DB 28 2000 367.0 367.0 35.0 SSOP DB 28 2000 367.0 367.0 38.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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