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PARALLEL

SERIAL

INPUT LATCH

PLL

TIMING and

CONTROL

O+

O-

DEN

TCLK

(30 MHz to 66 MHz)

SYNC1

SYNC2

SERIAL

PARALLEL

OUTPUT LATCH

PLL

TIMING and

CONTROL

I+

I-

LVDS

OUT

REFCLK

LOCK

CLOCK

RECOVERY

REN

(30 MHz to 66 MHz)

TCLK_R/F

RCLK_R/F

DS92LV1023E

10-Bit Deserializer

RCLK

DS92LV1023E

www.ti.com

SNLS187B –MARCH 2005–REVISED APRIL 2013

DS92LV1023E 30-66 MHz 10 Bit Bus LVDS Serializer

Check for Samples: DS92LV1023E

FEATURES

DESCRIPTION

The DS92LV1023E is a 300 to 660 Mb/s serializer for

• 30–66 MHz Single 10:1 Serializer with 300–660

high-speed unidirectional serial data transmission

Mb/s Throughput

over FR-4 printed circuit board backplanes and

• Robust Bus LVDS Serial Data Transmission

balanced copper cables. It transforms a 10-bit wide

with Embedded Clock for Exceptional Noise

parallel LVCMOS/LVTTL data bus into a single high

Immunity and Low EMI

speed Bus LVDS serial data stream with embedded

clock. This single serial data stream simplifies PCB

• >10 kV HBM ESD Protection on Bus LVDS

design and reduces PCB cost by narrowing data

Output Pins

paths that in turn reduce PCB size and number of

• Transition Every Data Transfer Cycle Ensured

layers. The single serial data stream also reduces

• Low Power Consumption < 250 mW (typ) at 66

cable size, the number of connectors, and eliminates

MHz

clock-to-data and data-to-data skew.

• Single Differential Pair Eliminates Multichannel

The DS92LV1023E works well with any TI

Skew

Semiconductor's Bus LVDS 10–bit deserializer within

its specified frequency operating range. It features

• Flow-Through Pinout for Easy PCB Layout

exceptional ESD protection, pin selectable edge

• Programmable Edge Trigger on Clock

trigger on clock, and high impedance outputs in

• High Impedance on Driver Outputs When

power down mode.

Power is Off

The DS92LV1023E was designed with the flow-

• Bus LVDS Serial Output Rated for 27Ω Load

through pinout and is available in a space saving

• Small 28-Lead SSOP Package

28–lead SSOP package.

Block Diagrams

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (20 pages)

PAGE 1
DS92LV1023E www.ti.com SNLS187B – MARCH 2005 – REVISED APRIL 2013 DS92LV1023E 30-66 MHz 10 Bit Bus LVDS Serializer Check for Samples: DS92LV1023E FEATURES DESCRIPTION • The DS92LV1023E is a 300 to 660 Mb/s serializer for high-speed unidirectional serial data transmission over FR-4 printed circuit board backplanes and balanced copper cables. It transforms a 10-bit wide parallel LVCMOS/LVTTL data bus into a single high speed Bus LVDS serial data stream with embedded clock.
PAGE 2
DS92LV1023E SNLS187B – MARCH 2005 – REVISED APRIL 2013 www.ti.com Functional Description The DS92LV1023E is a 10-bit Serializer device which together with a compatible deserializer (i.e. DS92LV1224) forms a chipset designed to transmit data over FR-4 printed circuit board backplanes and balanced copper cables at clock speeds from 30 to 66 MHz. The chipset has three active states of operation: Initialization, Data Transfer, and Resynchronization; and two passive states: Powerdown and TRI-STATE.
PAGE 3
DS92LV1023E www.ti.com SNLS187B – MARCH 2005 – REVISED APRIL 2013 Data Transfer After initialization, the Serializer will accept data from inputs DIN0–DIN9. The Serializer uses the TCLK input to latch incoming Data. The TCLK_R/F pin selects which edge the Serializer uses to strobe incoming data. TCLK_R/F high selects the rising edge for clocking data and low selects the falling edge. If either of the SYNC inputs is high for 5*TCLK cycles, the data at DIN0-DIN9 is ignored regardless of clock edge.
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DS92LV1023E SNLS187B – MARCH 2005 – REVISED APRIL 2013 www.ti.com If a specific pattern is repetitive, the Deserializer could enter “false lock” - falsely recognizing the data pattern as the clocking bits. We refer to such a pattern as a repetitive multi-transition, RMT. This occurs when more than one Low-High transition takes place in a clock cycle over multiple cycles. This occurs when any bit, except DIN 9, is held at a low state and the adjacent bit is held high, creating a 0-1 transition.
PAGE 5
DS92LV1023E www.ti.com SNLS187B – MARCH 2005 – REVISED APRIL 2013 TRI-STATE The Serializer enters TRI-STATE when the DEN pin is driven low. This puts both driver output pins (DO+ and DO−) into TRI-STATE. When you drive DEN high, the Serializer returns to the previous state, as long as all other control pins remain static (SYNC1, SYNC2, PWRDN, TCLK_R/F). When you drive the REN pin low, the Deserializer enters TRI-STATE. Consequently, the receiver output pins (ROUT0–ROUT9) and RCLK will enter TRI-STATE.
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DS92LV1023E SNLS187B – MARCH 2005 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) (3) (4) −0.3V to +4V Supply Voltage (VCC) −0.3V to (VCC +0.3V) LVCMOS/LVTTL Input Voltage −0.3V to +3.
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DS92LV1023E www.ti.com SNLS187B – MARCH 2005 – REVISED APRIL 2013 Electrical Characteristics (1) (2) Over recommended operating supply and temperature ranges unless otherwise specified. Parameter Test Conditions Min Typ Max Units SERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (apply to DIN0-9, TCLK, PWRDN, TCLK_R/F, SYNC1, SYNC2, DEN) VIH High Level Input Voltage 2.0 VCC V VIL Low Level Input Voltage GND 0.8 V VCL Input Clamp Voltage ICL = −18 mA -0.86 −1.
PAGE 8
DS92LV1023E SNLS187B – MARCH 2005 – REVISED APRIL 2013 www.ti.com Serializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified.
PAGE 9
DS92LV1023E www.ti.com SNLS187B – MARCH 2005 – REVISED APRIL 2013 Timing shown for TCLK_R/F = LOW Figure 5. Serializer Setup/Hold Times Figure 6. Serializer TRI-STATE Test Circuit and Timing Figure 7.
PAGE 10
DS92LV1023E SNLS187B – MARCH 2005 – REVISED APRIL 2013 www.ti.com Figure 8. SYNC Timing Delays Figure 9.
PAGE 11
DS92LV1023E www.ti.com SNLS187B – MARCH 2005 – REVISED APRIL 2013 SW - Setup and Hold Time (Internal Data Sampling Window) tDJIT - Serializer Output Bit Position Jitter that results from Jitter on TCLK tRNM = Receiver Noise Margin Time Figure 10. Receiver Bus LVDS Input Skew Margin VOD = (DO+)–(DO−). Differential output signal is shown as (DO+)–(DO−), device in Data Transfer mode. Figure 11.
PAGE 12
DS92LV1023E SNLS187B – MARCH 2005 – REVISED APRIL 2013 www.ti.com APPLICATION INFORMATION USING THE SERIALIZER AND DESERIALIZER CHIPSET The Serializer and Deserializer chipset is an easy to use transmitter and receiver pair that sends 10 bits of parallel LVTTL data over a serial Bus LVDS link up to 660 Mbps. An on-board PLL serializes the input data and embeds two clock bits within the data stream.
PAGE 13
DS92LV1023E www.ti.com SNLS187B – MARCH 2005 – REVISED APRIL 2013 Figure 12. Random Lock Hot Insertion Pin Diagram Figure 13.
PAGE 14
DS92LV1023E SNLS187B – MARCH 2005 – REVISED APRIL 2013 www.ti.com Serializer Pin Description Pin Name I/O Pin No. DIN I 3–12 Data Input. LVTTL levels inputs. Data on these pins are loaded into a 10-bit input register. TCLK_R/F I 13 Transmit Clock Rising/Falling strobe select. LVTTL level input. Selects TCLK active edge for strobing of DIN data. High selects rising edge. Low selects falling edge. DO+ O 22 + Serial Data Output. Non-inverting Bus LVDS differential output.
PAGE 15
DS92LV1023E www.ti.com SNLS187B – MARCH 2005 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision A (April 2013) to Revision B • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
PAGE 16
PACKAGE OPTION ADDENDUM www.ti.
PAGE 17
PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device DS92LV1023EMQX/NOP B Package Package Pins Type Drawing SSOP DB 28 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 8.4 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.7 2.4 12.0 16.
PAGE 18
PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS92LV1023EMQX/NOPB SSOP DB 28 2000 367.0 367.0 38.
PAGE 19
MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 20
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