DS92LV1212 DS92LV1212 16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery Literature Number: SNLS050
DS92LV1212 16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery General Description Features The DS92LV1212 is an upgrade of the DS92LV1210. It maintains all of the features of the DS92LV1210 with the additional capability of locking to the incoming data stream without the need of SYNC patterns. This makes the DS92LV1212 useful in applications where the Deserializer must be operated “open-loop” — without a feedback path from the Deserializer to the Serializer.
Block Diagram (Continued) Application DS100982-2 formation. When the Deserializer locks to the Bus LVDS clock, the LOCK output will go low. When LOCK is low the Deserializer outputs represent incoming Bus LVDS data. Functional Description The DS92LV1212 is a 10-bit Deserializer chip designed to receive data over a heavily loaded differential backplanes at clock speeds from 16 MHz to 40 MHz. It may also be used to receive data over Unshielded Twisted Pair (UTP) cable.
Random Lock Initialization and Resynchronization Powerdown The Powerdown state is a low power sleep mode that can be used to reduce power when there is no data to be transferred. Powerdown is entered when PWRDN and REN are driven low on the Deserializer. In Powerdown, the PLL is stopped and the outputs go into TRI-STATE, disabling load current and also reducing supply current to the milliamp range. To exit Powerdown, PWRDN is driven high.
RMT Patterns DS100982-23 DS100982-24 DIN0 Held Low-DIN1 Held High Creates an RMT Pattern DIN4 Held Low-DIN5 Held High Creates an RMT Pattern DS100982-25 DIN8 Held Low-DIN9 Held High Creates an RMT Pattern Order Numbers www.national.
Absolute Maximum Ratings (Note 1) Package Derating: 28L SSOP ESD Rating (HBM) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) −0.3V to +4V CMOS/TTL Input Voltage −0.3V to (VCC +0.3V) CMOS/TTL Output Voltage −0.3V to (VCC +0.3V) Bus LVDS Receiver Input Voltage −0.3V to +3.
Deserializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Pin/Freq.
AC Timing Diagrams and Test Circuits DS100982-4 FIGURE 1. “Worst Case” Deserializer ICC Test Pattern DS100982-6 FIGURE 2. Deserializer CMOS/TTL Output Load and Transition Times DS100982-11 FIGURE 3. Serializer Delay DS100982-12 FIGURE 4. Deserializer Delay 7 www.national.
AC Timing Diagrams and Test Circuits (Continued) DS100982-13 Timing shown for RCLK_R/F = LOW Duty Cycle (tRDC) = FIGURE 5. Deserializer Setup and Hold Times DS100982-14 FIGURE 6. Deserializer TRI-STATE Test Circuit and Timing www.national.
AC Timing Diagrams and Test Circuits (Continued) DS100982-15 FIGURE 7. Deserializer PLL Lock Times and PWRDN TRI-STATE Delays DS100982-22 FIGURE 8. Deserializer PLL Lock Time from SyncPAT 9 www.national.
AC Timing Diagrams and Test Circuits (Continued) DS100982-21 SW - Setup and Hold Time (Internal data sampling window) tJIT- Serializer Output Bit Position Jitter tRSM = Receiver Sampling Margin Time FIGURE 9. Receiver Bus LVDS Input Skew Margin While the Deserializer LOCK output is low, data at the Deserializer outputs (ROUT0-9) is valid except for the specific case of loss of lock during transmission.
Application Information 50 Ohms. This load is further lowered by the addition of multiple Deserializers. Adding up to 20 Deserializers to the bus (depending upon spacing) will lower the total load to about 27 Ohms (54 Ohm bus). The Serializer is designed for DC loads between 27 and 100 Ohms. The Serializer and Deserializer can also be used in point-to-point configuration of a backplane, PCB trace or through a twisted pair cable.
Deserializer Pin Description Pin Name (Continued) I/O No. RCLK_R/F I 2 Recovered Clock Rising/Falling strobe select. TTL level input. Selects RCLK active edge for strobing of ROUT data. High selects rising edge. Low selects falling edge. Description RI+ I 5 + Serial Data Input. Non-inverting Bus LVDS differential input. RI− I 6 − Serial Data Input. Inverting Bus LVDS differential input. PWRDN I 7 Powerdown. TTL level input. PWRDN driven low shuts down the PLL.
inches (millimeters) unless otherwise noted Order Number DS92LV1021TMSA or DS92LV1212TMSA NS Package Number MSA28 LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1.
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