Datasheet

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DS92LV18

www.ti.com

SNLS156E –SEPTEMBER 2003–REVISED APRIL 2013

DS92LV18 18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz

Check for Samples: DS92LV18

FEATURES

DESCRIPTION

The DS92LV18 Serializer/Deserializer (SERDES) pair

• 15–66 MHz 18:1/1:18 Serializer/Deserializer

transparently translates a 18–bit parallel bus into a

(2.376 Gbps Full Duplex Throughput)

BLVDS serial stream with embedded clock

• Independent Transmitter and Receiver

information. This single serial stream simplifies

Operation with Separate Clock, Enable, and

transferring a 18-bit, or less, bus over PCB traces

Power Down Pins

and cables by eliminating the skew problems

between parallel data and clock paths. It saves

• Hot Plug Protection (Power Up High

system cost by narrowing data paths that in turn

Impedance) and Synchronization (Receiver

reduce PCB layers, cable width, and connector size

Locks to Random Data)

and pins.

• Wide ±5% Reference Clock Frequency

This SERDES pair includes built-in system and

Tolerance for Easy System Design Using

device test capability. The line loopback feature

Locally-Generated Clocks

enables the user to check the integrity of the serial

• Line and Local Loopback Modes

data transmission paths of the transmitter and

• Robust BLVDS Serial Transmission Across

receiver while deserializing the serial data to parallel

Backplanes and Cables for Low EMI

data at the receiver outputs. The local loopback

feature enables the user to check the integrity of the

• No External Coding Required

transceiver from the local parallel-bus side.

• Internal PLL, No External PLL Components

The DS92LV18 incorporates modified BLVDS

Required

signaling on the high-speed I/O. BLVDS provides a

• Single +3.3V Power Supply

low power and low noise environment for reliably

• Low Power: 90mA (typ) Transmitter, 100mA

transferring data over a serial transmission path. The

(typ) at 66 MHz with PRBS-15 Pattern

equal and opposite currents through the differential

data path control EMI by coupling the resulting

• ±100 mV Receiver Input Threshold

fringing fields together.

• Loss of Lock Detection and Reporting Pin

• Industrial −40 to +85°C Temperature Range

• >2.0kV HBM ESD

• Compact, Standard 80-Pin LQFP Package

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (26 pages)

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DS92LV18 www.ti.com SNLS156E – SEPTEMBER 2003 – REVISED APRIL 2013 DS92LV18 18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz Check for Samples: DS92LV18 FEATURES DESCRIPTION • The DS92LV18 Serializer/Deserializer (SERDES) pair transparently translates a 18–bit parallel bus into a BLVDS serial stream with embedded clock information.
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DS92LV18 SNLS156E – SEPTEMBER 2003 – REVISED APRIL 2013 www.ti.com Block Diagram Figure 1. DS92LV18 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) −0.3V to +4V Supply Voltage (VCC) LVCMOS/LVTTL Input Voltage −0.3V to (VCC +0.3V) LVCMOS/LVTTL Output Voltage −0.3V to (VCC +0.
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DS92LV18 www.ti.com SNLS156E – SEPTEMBER 2003 – REVISED APRIL 2013 Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Pin/Freq. Min Typ (1) Max Units 2.0 VCC V GND 0.8 V −1.5 V LVCMOS/LVTTL DC Specifications VIH High Level Input Voltage VIL Low Level Input Voltage VCL Input Clamp Voltage ICL = −18 mA IIN Input Current VIN = 0V or 3.
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DS92LV18 SNLS156E – SEPTEMBER 2003 – REVISED APRIL 2013 www.ti.com Serializer Timing Requirements for TCLK Over recommended operating supply and temperature ranges unless otherwise specified. Symbol (1) Parameter Conditions Min Typ Max Units tTCP Transmit Clock Period 15.2 T 66.7 ns tTCIH Transmit Clock High Time 0.4T 0.5T 0.6T ns tTCIL Transmit Clock Low Time 0.4T 0.5T 0.
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DS92LV18 www.ti.com SNLS156E – SEPTEMBER 2003 – REVISED APRIL 2013 Deserializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Pin/Freq. Min tRCP Receiver out Clock Period tRCP = tTCP RCLK 15.
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DS92LV18 SNLS156E – SEPTEMBER 2003 – REVISED APRIL 2013 www.ti.com AC Timing Diagrams and Test Circuits Figure 2. “Worst Case” Serializer ICC Test Pattern Figure 3. “Worst Case” Deserializer ICC Test Pattern Figure 4. Serializer Bus LVDS Distributed Output Load and Transition Times Figure 5. Deserializer CMOS/TTL Distributed Output Load and Transition Times Figure 6.
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DS92LV18 www.ti.com SNLS156E – SEPTEMBER 2003 – REVISED APRIL 2013 Figure 7. Serializer Setup/Hold Times Figure 8. Serializer TRI-STATE Test Circuit and Timing Figure 9.
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DS92LV18 SNLS156E – SEPTEMBER 2003 – REVISED APRIL 2013 www.ti.com Figure 10. SYNC Timing Delay Figure 11. Serializer Delay Figure 12. Deserializer Delay Figure 13.
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DS92LV18 www.ti.com SNLS156E – SEPTEMBER 2003 – REVISED APRIL 2013 Figure 14. Deserializer TRI-STATE Test Circuit and Timing Figure 15.
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DS92LV18 SNLS156E – SEPTEMBER 2003 – REVISED APRIL 2013 www.ti.com Figure 16. Deserializer PLL Lock Time from SYNCPAT Figure 17. Deterministic Jitter and Ideal Bit Position tRNMI-L is the noise margin on the left of the figure above. tRNMI-R is the noise margin on the right of the above figure. Figure 18.
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DS92LV18 www.ti.com SNLS156E – SEPTEMBER 2003 – REVISED APRIL 2013 VOD = (DO+)–(DO−). Differential output signal is shown as (DO+)–(DO−), device in Data Transfer mode. Figure 19. VOD Diagram 110 90 CURRENT (mA) 90 3.45V 80 70 60 3.30V 3.15V 50 50 40 30 10 10 20 30 40 50 60 70 FREQUENCY (MHz) Figure 20. Typical ICC vs. Frequency with PRBS-15 Pattern (Transmitter Only) 110 110 3.45V 100 CURRENT (mA) 90 70 60 3.30V 50 50 3.
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DS92LV18 SNLS156E – SEPTEMBER 2003 – REVISED APRIL 2013 www.ti.com FUNCTIONAL DESCRIPTION The DS92LV18 combines a serializer and deserializer onto a single chip. The serializer accepts an 18-bit LVCMOS or LVTTL data bus and transforms it into a BLVDS serial data stream with embedded clock information. The deserializer then recovers the clock and data to deliver the resulting 18-bit wide words to the output.
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DS92LV18 www.ti.com SNLS156E – SEPTEMBER 2003 – REVISED APRIL 2013 The Serializer transmits the data and clock bits (18+2 bits) at 20 times the TCLK frequency. For example, if TCLK is 60 MHz, the serial rate is 60 X 20= 1200 Mbps. Since only 18 bits are from input data, the serial 'payload' rate is 18 times the TCLK frequency. For instance, if TCLK = 60 MHz, the payload data rate is 60 X 18 = 1080 Mbps. TCLK is provided by the data source and must be in the range of 15 MHz to 66 MHz.
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DS92LV18 SNLS156E – SEPTEMBER 2003 – REVISED APRIL 2013 www.ti.com To bring the Serializer block out of the powerdown state, the system drives TPWDN high. When the Serializer exits Powerdown, its PLL must lock to TCLK before it is ready for the Initialization state. The system must then allow time for Initialization before data transfer can begin. TRI-STATE When the system drives the REN pin low, the Deserializer’s outputs enter TRI-STATE.
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DS92LV18 www.ti.com SNLS156E – SEPTEMBER 2003 – REVISED APRIL 2013 RECOVERING FROM LOCK LOSS In the case where the Serializer loses lock during data transmission, up to 5 cycles of data that were previously received could be invalid. This is due to a delay in the lock detection circuit. The lock detect circuit requires that invalid clock information be received 2 times in a row to indicate loss of lock. Since clock information has been lost, it is possible that data was also lost during these cycles.
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DS92LV18 SNLS156E – SEPTEMBER 2003 – REVISED APRIL 2013 www.ti.com Termination of the LVDS interconnect is required. For point-to-point applications, termination should be located at the load end. Nominal value is 100 Ohms to match the line's differential impedance. Place the resistor as close to the receiver inputs as possible to minimize the resulting stub between the termination resistor and receiver.
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DS92LV18 www.ti.
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DS92LV18 SNLS156E – SEPTEMBER 2003 – REVISED APRIL 2013 www.ti.com Pin Diagram Figure 23.
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DS92LV18 www.ti.com SNLS156E – SEPTEMBER 2003 – REVISED APRIL 2013 Table 1. PIN DESCRIPTIONS Pin # Pin Name I/O 1 RPWDN CMOS, I RPWDN = Low will put the Receiver in low power, stand-by, mode. Note: The Receiver PLL will lose lock. (1) 2 REN CMOS, I REN = Low will disable the Receiver outputs. Receiver PLL remains locked. (See LOCK pin description) (1) 4 REFCLK CMOS, I Frequency reference clock input for the receiver.
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DS92LV18 SNLS156E – SEPTEMBER 2003 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision D (April 2013) to Revision E • 20 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 16-Nov-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device DS92LV18TVVX/NOPB Package Package Pins Type Drawing LQFP PN 80 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 24.4 Pack Materials-Page 1 14.65 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 14.65 2.15 24.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS92LV18TVVX/NOPB LQFP PN 80 1000 367.0 367.0 45.
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MECHANICAL DATA MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996 PN (S-PQFP-G80) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 41 60 61 40 80 21 0,13 NOM 1 20 Gage Plane 9,50 TYP 12,20 SQ 11,80 14,20 SQ 13,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040135 / B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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