Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - deserialisers Channel Link II (LVCMOS) WQFN 60

DS92LV2411, DS92LV2412

www.ti.com

SNLS302C –MAY 2010–REVISED APRIL 2013

DS92LV2411/DS92LV2412 5-50MHz 24-Bit Channel Link II Serializer and Deserializer

Check for Samples: DS92LV2411, DS92LV2412

FEATURES

DESCRIPTION

The DS92LV2411 (Serializer) / DS92LV2412

• 24–Bit Data, 3–Bit Control, 5 – 50 MHz Clock

(Deserializer) chipset translates a parallel 24–bit

• Application Payloads up to 1.2 Gbps

LVCMOS data interface into a single high-speed CML

• AC Coupled Interconnects: STP up to 10 m or

serial interface with embedded clock information. This

Coax 20+ m

single serial stream eliminates skew issues between

clock and data, reduces connector size and

• 1.8V or 3.3V Compatible LVCMOS I/O Interface

interconnect cost for transferring a 24-bit, or less, bus

• Integrated Terminations on Ser and Des

over FR-4 printed circuit board backplanes,

• AT-SPEED BIST Mode and Reporting Pin

differential or coax cables.

• Configurable by Pins or I2C Compatible Serial

In addition to the 24-bit data bus interface, the

Control Bus

DS92LV2411/12 also features a 3-bit control bus for

slow speed signals. This allows implementing video

• Power down mode minimizes power

and display applications with up to 24–bits per pixel

dissipation

(RGB888).

• >8 kV HBM ESD Rating

Programmable transmit de-emphasis, receive

SERIALIZER — DS92LV2411

equalization, on-chip scrambling and DC balancing

• Supports Spread Spectrum Clocking (SSC) on

enables long distance transmission over lossy cables

inputs

and backplanes. The DS92LV2412 automatically

• Data scrambler for Reduced EMI

locks to incoming data without an external reference

clock or special sync patterns, providing easy “plug-

• DC-Balance Encoder for AC Coupling

and-go” or “hot plug” operation. EMI is minimized by

• Selectable Output V

and Adjustable De-

the use of low voltage differential signaling, receiver

emphasis

drive strength control, and spread spectrum clocking

DESERIALIZER — DS92LV2412

capability.

• Random Data Lock; no Reference Clock

The DS92LV2411/12 chipset is programmable though

Required

an I2C interface as well as through pins. A built-in

AT-SPEED BIST feature validates link integrity and

• Adjustable Input Receiver Equalization

may be used for system diagnostics.

• LOCK (Real Time Link Status) Reporting Pin

The DS92LV2411 is offered in a 48-pin WQFN and

• Selectable Spread Spectrum Clock Generation

the DS92LV2412 is offered in a 60-pin WQFN

(SSCG) and Output Slew Rate Control (OS) to

package. Both devices operate over the full industrial

Reduce EMI

temperature range of -40°C to +85°C.

APPLICATIONS

• Embedded Video and Display

• Medical Imaging

• Factory Automation

• Office Automation — Printer, Scanner

• Security and Video Surveillance

• General Purpose Data Communication

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (50 pages)

PAGE 1
DS92LV2411, DS92LV2412 www.ti.com SNLS302C – MAY 2010 – REVISED APRIL 2013 DS92LV2411/DS92LV2412 5-50MHz 24-Bit Channel Link II Serializer and Deserializer Check for Samples: DS92LV2411, DS92LV2412 FEATURES DESCRIPTION • • • The DS92LV2411 (Serializer) / DS92LV2412 (Deserializer) chipset translates a parallel 24–bit LVCMOS data interface into a single high-speed CML serial interface with embedded clock information.
PAGE 2
DS92LV2411, DS92LV2412 SNLS302C – MAY 2010 – REVISED APRIL 2013 www.ti.com Applications Diagram VDDIO VDDn (1.8V or 3.3V) 1.8V DI[7:0] DI[15:8] DI[23:16] CI1 CI2 CI3 CLKIN Graphic Processor OR Video Imager OR ASIC/FPGA DO[7:0] DO[15:8] DO[23:16] CO1 CO2 CO3 CLKOUT Channel Link II 1 Pair / AC Coupled 0.1 PF 0.
PAGE 3
DS92LV2411, DS92LV2412 www.ti.
PAGE 4
DS92LV2411, DS92LV2412 SNLS302C – MAY 2010 – REVISED APRIL 2013 www.ti.com DS92LV2411 Serializer PIN DESCRIPTIONS(1) (continued) Pin Name Pin # I/O, Type CI2 3 I, LVCMOS w/ pull-down Description Control Signal Input For Display/Video Application: CI2 = Horizontal Sync Input Control signal pulse width must be 3 clocks or longer to be transmitted when the Control Signal Filter is enabled (CONFIG[1:0] = 01).
PAGE 5
DS92LV2411, DS92LV2412 www.ti.com SNLS302C – MAY 2010 – REVISED APRIL 2013 DS92LV2411 Serializer PIN DESCRIPTIONS(1) (continued) Pin Name Pin # I/O, Type Description Channel-Link II — CML Serial Interface DOUT+ 20 O, CML Non–Inverting Output. The output must be AC Coupled with a 0.1 µF capacitor. DOUT- 19 O, CML Inverting Output. The output must be AC Coupled with a 0.1 µF capacitor. VDDL 7 Power Logic Power, 1.8 V ±5% VDDP 14 Power PLL Power, 1.
PAGE 6
DS92LV2411, DS92LV2412 SNLS302C – MAY 2010 – REVISED APRIL 2013 www.ti.
PAGE 7
DS92LV2411, DS92LV2412 www.ti.com SNLS302C – MAY 2010 – REVISED APRIL 2013 DS92LV2412 Deserializer PIN DESCRIPTIONS (1) Pin Name Pin # I/O, Type Description LVCMOS Parallel Interface DO[7:0] 33, 34, 35, 36, 37, 39, 40, 41 I, STRAP, O, LVCMOS Parallel Interface Data Output Pins For 8–bit RED Display: DO7 = R7 – MSB, DO0 = R0 – LSB. In power-down (PDB = 0), outputs are controlled by the OSS_SEL (See Table 8). These pins are inputs during power-up (See STRAP Inputs).
PAGE 8
DS92LV2411, DS92LV2412 SNLS302C – MAY 2010 – REVISED APRIL 2013 www.ti.com DS92LV2412 Deserializer PIN DESCRIPTIONS(1) (continued) Pin Name Pin # I/O, Type LF_MODE 12 [DO20] STRAP I, LVCMOS w/ pull-down SSCG Low Frequency Mode Only required when SSCG is enabled, otherwise LF_MODE condition is a DON’T CARE (X). LF_MODE = 1, SSCG in low frequency mode (CLK = 5-20 MHz) LF_MODE = 0, SSCG in high frequency mode (CLK = 20-50 MHz) This can also be controlled by I2C register access.
PAGE 9
DS92LV2411, DS92LV2412 www.ti.com SNLS302C – MAY 2010 – REVISED APRIL 2013 DS92LV2412 Deserializer PIN DESCRIPTIONS(1) (continued) Pin Name NC Pin # I/O, Type 1, 15, 16, 30, 31, 45, 46, 60 Description Not Connected Leave pin open (float) Channel-Link II — CML Serial Interface RIN+ 49 I, CML True Input. The input must be AC Coupled with a 0.1 μF capacitor. RIN- 50 I, CML Inverting Input. The input must be AC Coupled with a 0.1 μF capacitor.
PAGE 10
DS92LV2411, DS92LV2412 SNLS302C – MAY 2010 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) −0.3V to +2.5V Supply Voltage – VDDn (1.8V) −0.3V to +4.0V Supply Voltage – VDDIO −0.3V to (VDDIO + 0.3V) LVCMOS I/O Voltage Receiver Input Voltage −0.3V to (VDD + 0.
PAGE 11
DS92LV2411, DS92LV2412 www.ti.com SNLS302C – MAY 2010 – REVISED APRIL 2013 SERIALIZER DC ELECTRICAL CHARACTERISTICS Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3) Symbol Parameter Conditons Pin/Freq. Min Typ Maz Units LVCMOS INPUT DC SPECIFICATIONS VDDIO = 3.0 to 3.6V VIH High Level Input Voltage VIL Low Level Input Voltage IIN Input Current VDDIO = 1.71 to 1.89V VDDIO = 3.0 to 3.6V VDDIO = 1.71 to 1.89V VIN = 0V or VDDIO VDDIO = 3.0 to 3.
PAGE 12
DS92LV2411, DS92LV2412 SNLS302C – MAY 2010 – REVISED APRIL 2013 www.ti.com SERIALIZER DC ELECTRICAL CHARACTERISTICS (continued) Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3) Symbol Parameter Conditons Pin/Freq. Min Typ Maz Units SUPPLY CURRENT IDDT1 IDDIOT1 Serializer Supply Current Checker Board VDD = 1.89V (includes load current) RL = Pattern, De-emph VDDIO = 1.89V 100 Ω, CLKIN = 50 MHz = 3kΩ, VODSEL VDDIO = 3.
PAGE 13
DS92LV2411, DS92LV2412 www.ti.com SNLS302C – MAY 2010 – REVISED APRIL 2013 DESERIALIZER ELECTRICAL CHARACTERISTICS (continued) Over recommended operating supply and temperature ranges unless otherwise specified.(1) (2) (3) Symbol Parameter Conditons Pin/Freq.
PAGE 14
DS92LV2411, DS92LV2412 SNLS302C – MAY 2010 – REVISED APRIL 2013 www.ti.com Serializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified.
PAGE 15
DS92LV2411, DS92LV2412 www.ti.com SNLS302C – MAY 2010 – REVISED APRIL 2013 Deserializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Pin/Freq.
PAGE 16
DS92LV2411, DS92LV2412 SNLS302C – MAY 2010 – REVISED APRIL 2013 www.ti.com Recommended Timing for the Serial Control Bus Over recommended operating supply and temperature ranges unless otherwise specified. Symbol fSCL Parameter SCL Clock Frequency tLOW SCL Low Period tHIGH tSU:STA tHD;DAT tSU;DAT tSU;STO tBUF tr tf Min Typ Max Units Standard Mode 100 kHz Fast Mode 400 kHz Standard Mode 4.7 µs Fast Mode 1.3 µs Standard Mode 4.0 µs Fast Mode 0.
PAGE 17
DS92LV2411, DS92LV2412 www.ti.com SNLS302C – MAY 2010 – REVISED APRIL 2013 AC Timing Diagrams and Test Circuits A A' CA Scope 50: 50: CB B B' 50: 50: Single-Ended Figure 6. Serializer Test Circuit DOUT+ VOD- VOD+ DOUT- VOS VOD+ (DOUT+) - (DOUT+) 0V VODp-p VOD- Differential GND Figure 7. Serializer Output Waveforms +VOD 80% 0V (DOUT+) - (DOUT-) 20% -VOD tLLHT tLHLT Figure 8.
PAGE 18
DS92LV2411, DS92LV2412 SNLS302C – MAY 2010 – REVISED APRIL 2013 www.ti.com PDB CLKIN 1/2 VDDIO "X" active tPLD DOUT (Diff.) Driver On Driver OFF, VOD = 0V Figure 10. Serializer Lock Time 1/2 VDDIO PDB CLKIN active "X" tXZD DOUT (Diff.) active Driver OFF, VOD = 0V Figure 11. Serializer Disable Time DIN[23:0], CI1,CI2,CI3 SYMBOL N SYMBOL N+1 tSD CLKIN (RFB = L) START BIT STOP START BIT BIT STOP BIT DOUT (Diff.) SYMBOL N-1 SYMBOL N Figure 12.
PAGE 19
DS92LV2411, DS92LV2412 www.ti.com SNLS302C – MAY 2010 – REVISED APRIL 2013 VDDIO CLKIN/ CLKOUT w/ RFB = L GND VDDIO DI/DO (odd), CI2/CO2, CI3/CO3 GND VDDIO DI/DO (even), CI1/CO1 GND Figure 14. Checkerboard Data Pattern VDDIO 80% 20% GND tCLH tCHL Figure 15. Deserializer LVCMOS Transition Times START BIT STOP START BIT BIT STOP BIT RIN (Diff.) SYMBOL N SYMBOL N+1 tDD CLKOUT (RFB = L) DO[23:0], CO1,CO2,CO3 SYMBOL N-2 SYMBOL N-1 SYMBOL N Figure 16.
PAGE 20
DS92LV2411, DS92LV2412 SNLS302C – MAY 2010 – REVISED APRIL 2013 PDB www.ti.com 2.0V 0.8V RIN (Diff.) 'RQ¶W &DUH tDDLT LOCK TRI-STATE or LOW Z or L tRxZ DO[23:0], CO1,CO2,CO3 TRI-STATE or LOW or Pulled Up CLKOUT (RFB = L) Z or L or PU TRI-STATE or LOW OFF Z or L IN LOCK TIME ACTIVE OFF Figure 18. Deserializer PLL Lock Times and PDB TRI-STATE Delay VDDIO CLKOUT w/RFB = H 1/2 VDDIO GND VDDIO DO[23:0], CO1,CO2,CO3 1/2 VDDIO 1/2 VDDIO GND tROS tROH Figure 19.
PAGE 21
DS92LV2411, DS92LV2412 www.ti.com SNLS302C – MAY 2010 – REVISED APRIL 2013 BISTEN 1/2 VDDIO tPASS PASS (w/ errors) 1/2 VDDIO Current BIST Test - Toggle on Error Prior BIST Result Result Held Figure 22. BIST PASS Waveform SDA tLOW tf tHD;STA tf tr tr tBUF tSP SCL tSU;STA tHD;STA tHIGH tHD;DAT START tSU;STO tSU;DAT STOP REPEATED START START Figure 23.
PAGE 22
DS92LV2411, DS92LV2412 SNLS302C – MAY 2010 – REVISED APRIL 2013 www.ti.com Table 1. DS92LV2411 Ser Modes CONFIG1 CONFIG0 MODE DES DEVICE L L Normal Mode, Control Signal Filter disabled DS92LV2412, DS92LV2412, DS92LV0422, DS92LV0412 L H Normal Mode, Control Signal Filter enabled DS92LV2412, DS92LV2412, DS92LV0422, DS92LV0412 H L Reverse Compatibility Mode DS90UR124, DS99R124 H H Reverse Compatibility Mode DS90C124 Table 2.
PAGE 23
DS92LV2411, DS92LV2412 www.ti.com SNLS302C – MAY 2010 – REVISED APRIL 2013 Ser — Spread Spectrum Compatibility The Ser CLKIN is capable of tracking spread spectrum clocking (SSC) from a host source. The CLKIN will accept spread spectrum tracking up to 35 kHz modulation and ±0.5, ±1 or ±2% deviations (center spread). The maximum conditions for the CLKIN input are: a modulation frequency of 35 kHz and amplitude deviations of ±2% (4% total).
PAGE 24
DS92LV2411, DS92LV2412 SNLS302C – MAY 2010 – REVISED APRIL 2013 www.ti.com Power Saving Features Ser — Power Down Feature (PDB) The Ser has a PDB input pin to ENABLE or POWER DOWN the device. This pin is controlled by the host and is used to save power, disabling the link when the it is not needed. In the POWER DOWN mode, the high-speed driver outputs are both pulled to VDD and present a 0V VOD state. Note – in POWER DOWN, the optional Serial Bus Control Registers are RESET.
PAGE 25
DS92LV2411, DS92LV2412 www.ti.com SNLS302C – MAY 2010 – REVISED APRIL 2013 Table 5. Receiver Equalization Configuration Table (continued) INPUTS EQ3 EQ2 EQ1 EQ0 Effect L H H H ~6 dB H L L H ~7.5 dB H L H H ~9 dB H H L H ~10.5 dB H H H H ~12 dB X X X L OFF* * Default Setting is EQ = Off EMI Reduction Features Des — Output Slew Rate Select (OS_CLKOUT/OS_DATA) The parallel data outputs and clock outputs of the deserializer feature selectable output slew rates.
PAGE 26
DS92LV2411, DS92LV2412 SNLS302C – MAY 2010 – REVISED APRIL 2013 www.ti.com Table 7. SSCG Configuration (LF_MODE = H) — Des Output SSC[3:0] Inputs LH_MODE = H (5 - 20 MHz) Result SSC3 SSC2 SSC1 SSC0 fdev (%) fmod (kHz) L L L L L L L NA Disable H ±0.5 L L H L ±1.0 L L H H ±1.5 L H L L ±2.0 L H L H ±0.5 L H H L ±1.0 L H H H ±1.5 H L L L ±2.0 H L L H ±0.5 H L H L ±1.0 H L H H ±1.5 H H L L ±2.0 H H L H ±0.5 H H H L ±1.
PAGE 27
DS92LV2411, DS92LV2412 www.ti.com SNLS302C – MAY 2010 – REVISED APRIL 2013 Des — CLOCK-DATA RECOVERY STATUS FLAG (LOCK) and OUTPUT STATE SELECT (OSS_SEL) When PDB is driven HIGH, the CDR PLL begins locking to the serial input and LOCK goes from TRI-STATE to LOW (depending on the value of the OSS_SEL setting).
PAGE 28
DS92LV2411, DS92LV2412 SNLS302C – MAY 2010 – REVISED APRIL 2013 www.ti.com PDB (DES) RIN (Diff.) LOCK DO[23:0], CO1,CO2,CO3 CLKOUT* (DES) active serial stream X H Z H L L L L L L Z Z Z Z Z Locking OFF Active Active C0 or C1 Error In Bit Stream (Loss of LOCK) OFF CONDITIONS: * RFB = L, and OSS_SEL Strap = L Figure 26. Des Outputs with Output State Select Low (OSS_SEL = L) PDB (DES) RIN (Diff.
PAGE 29
DS92LV2411, DS92LV2412 www.ti.com SNLS302C – MAY 2010 – REVISED APRIL 2013 Table 10. OSC_SEL (Oscillator) Configuration (continued) OSC_SEL[2:0] INPUTS OSC_SEL2 CLKOUT Oscillator Frequency OSC_SEL1 OSC_SEL0 H L H 10 MHz ±40% H H L 8.3 MHz ±40% H H H 6.3 MHz ±40% PDB (DES) RIN (Diff.
PAGE 30
DS92LV2411, DS92LV2412 SNLS302C – MAY 2010 – REVISED APRIL 2013 PDB www.ti.com 2.0V LOCK OP_ LOW SET (Strap pin) User controlled User controlled OP_ LOW RELEASE/SET (Register) DO[23:0], CO3, CO2, CO1 TRISTATE ACTIVE ACTIVE CLKOUT TRISTATE ACTIVE ACTIVE Figure 29. OP_LOW Auto Set PDB 2.0V LOCK OP_LOW SET (Strap pin) User controlled User controlled OP_ LOW RELEASE/SET (Register) DO[23:0], CO3, CO2, CO1 TRISTATE ACTIVE CLKOUT TRISTATE ACTIVE Figure 30.
PAGE 31
DS92LV2411, DS92LV2412 www.ti.com SNLS302C – MAY 2010 – REVISED APRIL 2013 Des — SSCG Low Frequency Optimization (LF_Mode) Text to come. This feature may be controlled by the external pin or by Register. Des — Strap Input Pins Configuration of the device maybe done via configuration input pins and the STRAP input pins, or via the Serial Control Bus. The STRAP input pins share select parallel bus output pins. They are used to load in configuration values during the initial power up sequence of the device.
PAGE 32
DS92LV2411, DS92LV2412 SNLS302C – MAY 2010 – REVISED APRIL 2013 www.ti.com Normal Step 1: SER in BIST BIST Wait Step 2: Wait, DES in BIST BIST start Step 3: DES in Normal Mode - check PASS BIST stop Step 4: SER in Normal Figure 31. BIST Mode Flow Diagram BER Calculations It • • • is possible to calculate the approximate Bit Error Rate (BER).
PAGE 33
DS92LV2411, DS92LV2412 www.ti.com SNLS302C – MAY 2010 – REVISED APRIL 2013 Optional Serial Bus Control The Ser and Des may also be configured by the use of a serial control bus that is I2C protocol compatible. By default, the I2C reg_0x00'h is set to 00'h and all configuration is set by control/strap pins. A write of 01'h to reg_0x00'h will enable/allow configuration by registers; this will override the control/strap pins.
PAGE 34
DS92LV2411, DS92LV2412 SNLS302C – MAY 2010 – REVISED APRIL 2013 www.ti.com Table 11. ID[x] Resistor Value – DS92LV2411 Ser Resistor RID kΩ Address 7'b Address 8'b 0 appended (WRITE) 0.47 7b' 110 1001 (h'69) 8b' 1101 0010 (h'D2) 2.7 7b' 110 1010 (h'6A) 8b' 1101 0100 (h'D4) 8.2 7b' 110 1011 (h'6B) 8b' 1101 0110 (h'D6) Open 7b' 110 1110 (h'6E) 8b' 1101 1100 (h'DC) Table 12. ID[x] Resistor Value – DS92LV2412 Des Resistor RID kΩ Address 7'b Address 8'b 0 appended (WRITE) 0.
PAGE 35
DS92LV2411, DS92LV2412 www.ti.com SNLS302C – MAY 2010 – REVISED APRIL 2013 Table 13.
PAGE 36
DS92LV2411, DS92LV2412 SNLS302C – MAY 2010 – REVISED APRIL 2013 www.ti.com Table 14.
PAGE 37
DS92LV2411, DS92LV2412 www.ti.com SNLS302C – MAY 2010 – REVISED APRIL 2013 Table 14.
PAGE 38
DS92LV2411, DS92LV2412 SNLS302C – MAY 2010 – REVISED APRIL 2013 www.ti.com APPLICATIONS INFORMATION DISPLAY APPLICATION The DS92LV2411/DS92LV2412 chipset is intended for interface between a host (graphics processor) and a Display. It supports an 24-bit color depth (RGB888). In a RGB888 application, 24 color bits (D[23:0), Pixel Clock (CLKIN) and three control bits (C1, C2, C3) are supported across the serial link with CLK rates from 5 to 50 MHz. The chipset may also be used in 18-bit color applications.
PAGE 39
DS92LV2411, DS92LV2412 www.ti.com SNLS302C – MAY 2010 – REVISED APRIL 2013 DS92LV2411 (SER) VDDIO VDDIO C9 C7 FB1 C3 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DI9 DI10 DI11 DI12 DI13 DI14 DI15 LVCMOS Parallel Video Interface VDDTX VDDHS CI1 CI2 CI3 LVCMOS Control Interface BISTEN PDB C12 CONFIG1 CONFIG0 RFB C4 FB2 C5 FB3 C6 FB4 C8 C10 VDDP C11 VDDL C1 Serial Channel Link II Interface DOUT+ DOUTC2 DI16 DI17 DI18 DI19 DI20 DI21 DI22 DI23 CLKIN 1.8V VDDIO VODSEL De-Emph 1.
PAGE 40
DS92LV2411, DS92LV2412 SNLS302C – MAY 2010 – REVISED APRIL 2013 www.ti.com DS92LV2412 (DES) 1.8V VDDL C13 C11 VDDIO VDDIO C8 C3 VDDSC C12 C14 VDDIO C9 C4 VDDPR VDDIO C10 C5 VDDR C15 C6 VDDIR VDDIO EXAMPLE: STRAP Input Pull-Ups (10k) VDDCMLO C16 C7 C1 Serial Channel Link II Interface RIN+ RINCMF C2 C17 TP_A ROUT+ ROUT- TP_B Host Control BISTEN PDB C18 1.8V 10k ID[X] SCL SDA RID C1 - C2 = 0.1 PF C3 - C12 = 0.1 PF C13, C16 = 4.7 PF C17 = 4.
PAGE 41
DS92LV2411, DS92LV2412 www.ti.com SNLS302C – MAY 2010 – REVISED APRIL 2013 TRANSMISSION MEDIA The Ser/Des chip set is intended to be used in a point-to-point configuration, through a PCB trace, through twisted pair cable or through 50Ω coaxial cables. The Ser and Des provide internal terminations providing a clean signaling environment. The interconnect for the differential serial interface should present a differential impedance of 100Ω.
PAGE 42
DS92LV2411, DS92LV2412 SNLS302C – MAY 2010 – REVISED APRIL 2013 www.ti.com SERIAL INTERCONNECT GUIDELINES See AN-1108 (SNLA008) and AN-905 (SNLA035) for full details.
PAGE 43
DS92LV2411, DS92LV2412 www.ti.com SNLS302C – MAY 2010 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision B (April 2013) to Revision C • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
PAGE 44
PACKAGE OPTION ADDENDUM www.ti.
PAGE 45
PACKAGE OPTION ADDENDUM www.ti.com 16-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
PAGE 46
PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing DS92LV2411SQ/NOPB WQFN RHS 48 DS92LV2411SQE/NOPB WQFN RHS DS92LV2411SQX/NOPB WQFN RHS DS92LV2412SQ/NOPB WQFN DS92LV2412SQE/NOPB DS92LV2412SQX/NOPB SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.
PAGE 47
PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS92LV2411SQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 DS92LV2411SQE/NOPB WQFN RHS 48 250 213.0 191.0 55.0 DS92LV2411SQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 DS92LV2412SQ/NOPB WQFN NKB 60 1000 367.0 367.0 38.0 DS92LV2412SQE/NOPB WQFN NKB 60 250 213.0 191.0 55.
PAGE 48
PAGE 49
MECHANICAL DATA NKB0060B SQA60B (Rev B) www.ti.
PAGE 50
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.