Datasheet

DS92LV2411, DS92LV2412
SNLS302C –MAY 2010–REVISED APRIL 2013 www.ti.com
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
t
LHT
Ser Output Low-to-High R
L
= 100Ω, De-emphasis = disabled,
200 ps
Transition Time, Figure 8 VODSEL = 0
R
L
= 100Ω, De-emphasis = disabled,
200 ps
VODSEL = 1
t
HLT
Ser Output High-to-Low R
L
= 100Ω, De-emphasis = disabled,
200 ps
Transition Time, Figure 8 VODSEL = 0
R
L
= 100Ω, De-emphasis = disabled,
200 ps
VODSEL = 1
t
DIS
Input Data - Setup Time, DI[23:0], CI1, CI2, CI3 to CLKIN
2 ns
Figure 9
t
DIH
Input Data - Hold Time, CLKIN to DI[23:0], CI1, CI2, CI3
2 ns
Figure 9
t
XZD
Ser Ouput Active to OFF Delay,
8 15 ns
Figure 11
t
PLD
Serializer PLL Lock Time
(1)
, R
L
= 100Ω
1.4 10 ms
Figure 10
t
SD
Serializer Delay - Latency, R
L
= 100Ω
144*T 145*T ns
Figure 12
t
DJIT
Ser Output Total Jitter, R
L
= 100Ω, De-Emph = disabled,
0.28 UI
Figure 13 RANDOM pattern, CLKIN = 50 MHz
R
L
= 100Ω, De-Emph = disabled,
0.27 UI
RANDOM pattern, CLKIN = 43MHz
R
L
= 100Ω, De-Emph = disabled,
0.35 UI
RANDOM pattern, CLKIN = 5MHz
λ
STXBW
Serializer Jitter Transfer CLKIN = 50 MHz 3 MHz
Function -3 dB Bandwidth
CLKIN = 43 MHz 2.3 MHz
CLKIN = 20 MHz 1.3 MHz
CLKIN = 5MHz 650 kHz
δ
STX
Serializer Jitter Transfer CLKIN = 50 MHz 0.84 dB
Function Peaking
CLKIN = 43 MHz 0.83 dB
CLKIN = 20 MHz 0.83 dB
CLKIN = 5MHz 0.28 dB
(1) When the Serializer output is at TRI-STATE the Deserializer will lose PLL lock. Resynchronization / Relock must occur before data
transfer require t
PLD
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