Datasheet

DS92LV2411, DS92LV2412
www.ti.com SNLS302C –MAY 2010–REVISED APRIL 2013
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Pin/Freq. Min Typ Max Units
t
RCP
CLK Output Period t
RCP
= t
TCP
CLKOUT 20 T 200 ns
t
RDC
CLK Output Duty Cycle SSCG = OFF, 5 – 50MHz 43 50 57 %
SSCG = ON, 5 – 20 MHz 35 59 65 %
SSCG = ON, 20 – 50 MHz 40 53 60 %
t
CLH
LVCMOS V
DDIO
= 1.8V, CLKOUT/DO[23:0], CO1,
Low-to-High C
L
= 4pF, CO2, CO3 2.1 ns
Transition Time, Figure 15 OS_CLKOUT/DATA = L
V
DDIO
= 3.3V
C
L
= 4pF, 2.0 ns
OS_CLKOUT/DATA = H
t
CHL
LVCMOS V
DDIO
= 1.8V CLKOUT/DO[23:0], CO1,
High-to-Low C
L
= 4pF, CO2, CO3 1.6 ns
Transition Time, Figure 15 OS_CLKOUT/DATA = L
V
DDIO
= 3.3V
C
L
= 8 pF, 1.5 ns
OS_CLKOUT/DATA = H
t
ROS
Data Valid before CLKOUT – V
DDIO
= 1.71 to 1.89V or DO[23:0], CO1, CO2,
Set Up Time, Figure 19 V
DDIO
= 3.0 to 3.6V CO3 0.27 0.45 T
C
L
= 4pF (lumped load)
t
ROH
Data Valid after CLKOUT – Hold V
DDIO
= 1.71 to 1.89V or DO[23:0], CO1, CO2,
Time, Figure 19 V
DDIO
= 3.0 to 3.6V CO3 0.4 0.55 T
C
L
= 4pF (lumped load)
t
DDLT
Deserializer Lock Time, SSC[3:0] = OFF, CLKOUT = 5MHz
3 ms
Figure 18 See
(1)
SSC[3:0] = OFF, CLKOUT = 50MHz
4 ms
See
(1)
SSC[3:0] = ON, CLKOUT = 5MHz
30 ms
See
(1)
SSC[3:0] = ON, CLKOUT = 50MHz
6 ms
See
(1)
t
DD
Des Delay - Latency, Figure 16 CLKOUT = 5 to 50 MHz 139*T 140*T ns
t
DPJ
Des Period Jitter SSC[3:0] = OFF, CLKOUT = 5MHz 975 1700 ps
See
(2)
CLKOUT = 10MHz 500 1000 ps
CLKOUT = 50MHz 550 1250 ps
t
DCCJ
Des Cycle-to-Cycle Jitter SSC[3:0] = OFF, CLKOUT = 5MHz 675 1150 ps
See
(3)
CLKOUT = 10MHz 375 900 ps
CLKOUT = 50MHz 500 1150 ps
t
IIT
Des Input Jitter Tolerance, EQ = OFF, jitter freq <2MHz 0.9 UI
(4)
Figure 21 SSCG = OFF,
jitter freq >6MHz
0.5 UI
(4)
CLKOUT = 50 MHz
BIST Mode
t
PASS
BIST PASS Valid Time,
1 10 µs
BISTEN = 1, Figure 22
SSCG Mode
f
DEV
Spread Spectrum Under typical conditions CLKOUT = 5 to 50 MHz,
Clocking Deviation SSC[3:0] = ON ±0.5 ±2 %
Frequency
f
MOD
Spread Spectrum Under typical conditions CLKOUT = 5 to 50 MHz,
Clocking Modulation SSC[3:0] = ON 8 100 kHz
Frequency
(1) t
PLD
and t
DDLT
is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active clock.
(2) t
DPJ
is the maximum amount the period is allowed to deviate over many samples.
(3) t
DCCJ
is the maximum amount of jitter between adjacent clock cycles.
(4) UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1 / 28*CLK). The UI scales with clock frequency.
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