Datasheet

RFB
CLKIN
PDB
DS92LV2411 ± SERIALIZER
PLL
Timing and
Control
DOUT-
DOUT+
Input Latch
Parallel to Serial
DC Balance Encoder
De-Emph
VODSEL
DI[23:0]
CI1/DE
CI2/HS
CI3/VS
SCL
SCA
ID[x]
BISTEN
Pattern
Generator
CONFIG[1:0]
RIN-
DS92LV2412 ± DESERIALIZER
RIN+
Clock and
Data
Recovery
Timing and
Control
LOCK
CLKOUT
SSCG
Output Latch
Serial to Parallel
DC Balance Decoder
PASS
DO[23:0]
CO1/DE
CO2/HS
CO3/VS
Error
Detector
PDB
BISTEN
CMF
SCL
SCA
ID[x]
STRAP INPUT
LF_MODE
OS_CLKOUT
OS_DATA
OSS_SEL
RFB
EQ [3:0]
OSC_SEL [2:0]
SSC [3:0]
CONFIG [1:0]
MAP_SEL [1:0]
STRAP INPUT
OP_LOW
EQ
ROUT-
ROUT+
DI[7:0]
CI2
CI3
CLKIN
PDB
Serializer Deserializer
CI1
Graphic
Processor
Channel Link II
1 Pair / AC Coupled
DS92LV2411 DS92LV2412
100 ohm STP Cable
PASS
V
DDIO
PDB
SCL
SDA
RFB
VODSEL
DeEmph
BISTEN
BISTEN
LOCK
ID[x]
DAP DAP
CMF
0.1 PF 0.1 PF
SCL
SDA
ID[x]
STRAP pins
not shown
RIN+
RIN-
DOUT+
DOUT-
Optional Optional
(1.8V or 3.3V)(1.8V or 3.3V)
1.8V
1.8V
V
DDIO
V
DDn
V
DDn
ASIC/FPGA
OR
24-bit RGB
Display
ASIC/FPGA
OR
DI[15:8]
DI[23:16]
DO[7:0]
CO2
CO3
CLKOUT
CO1
DO[15:8]
DO[23:16]
Video
Imager
OR
DS92LV2411, DS92LV2412
SNLS302C –MAY 2010–REVISED APRIL 2013 www.ti.com
Applications Diagram
Figure 1.
Block Diagrams
Figure 2. Figure 3.
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