Datasheet

t
BIT
(1 UI)
Sampling
Window
Ideal Data
Bit End
Ideal Data Bit
Beginning
RxIN_TOL
Left
RxIN_TOL
Right
Ideal Center Position (t
BIT
/2)
t
RJIT
= RxIN_TOL (Left + Right)
V
TH
V
TL
0V
Sampling Window = 1 UI - t
RJIT
1/2 V
DDIO
GND
V
DDIO
GND
V
DDIO
t
ROS
t
ROH
CLKOUT
w/RFB = H
DO[23:0],
CO1,CO2,CO3
1/2 V
DDIO
1/2 V
DDIO
1/2 V
DDIO
GND
V
DDIO
GND
V
DDIO
t
ROS
t
ROH
CLKOUT
w/RFB = H
DO[23:0],
CO1,CO2,CO3
1/2 V
DDIO
1/2 V
DDIO
RIN
(Diff.)
Z or L or PU
Z or L
Z or L
TRI-STATE or LOW or Pulled Up
TRI-STATE or LOW
DO[23:0],
CO1,CO2,CO3
CLKOUT
(RFB = L)
TRI-STATE
or LOW
LOCK
'RQ¶W&DUH
t
RxZ
t
DDLT
PDB
2.0V
0.8V
IN LOCK TIMEOFF ACTIVE OFF
DS92LV2411, DS92LV2412
SNLS302C –MAY 2010–REVISED APRIL 2013 www.ti.com
Figure 18. Deserializer PLL Lock Times and PDB TRI-STATE Delay
Figure 19. Deserializer Output Data Valid (Setup and Hold) Times with SSCG = Off
Figure 20. Deserializer Output Data Valid (Setup and Hold) Times with SSCG = On
Figure 21. Receiver Input Jitter Tolerance
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