Datasheet

SCL
SDA
t
HD;STA
t
LOW
t
r
t
HD;DAT
t
HIGH
t
f
t
SU;DAT
t
SU;STA
t
SU;STO
t
f
START
REPEATED
START
STOP
t
HD;STA
START
t
SP
t
r
t
BUF
BISTEN
1/2 V
DDIO
PASS
(w/ errors)
t
PASS
1/2 V
DDIO
Prior BIST Result
Current BIST Test - Toggle on Error Result Held
DS92LV2411, DS92LV2412
www.ti.com SNLS302C –MAY 2010–REVISED APRIL 2013
Figure 22. BIST PASS Waveform
Figure 23. Serial Control Bus Timing Diagram
FUNCTIONAL DESCRIPTION
The DS92LV2411 / DS92LV2412 chipset transmits and receives 24-bits of data and 3 control signals over a
single serial CML pair operating at 140 Mbps to 1.4 Gbps. The serial stream also contains an embedded clock,
video control signals and the DC-balance information which enhances signal quality and supports AC coupling.
The Des can attain lock to a data stream without the use of a separate reference clock source, which greatly
simplifies system complexity and overall cost. The Des also synchronizes to the Ser regardless of the data
pattern, delivering true automatic “plug and lock” performance. It can lock to the incoming serial stream without
the need of special training patterns or sync characters. The Des recovers the clock and data by extracting the
embedded clock information, validating and then deserializing the incoming data stream providing a parallel
LVCMOS video bus to the display or ASIC/FPGA.
The DS92LV2411 / DS92LV2412 chipset can operate in 24-bit color depth (with DE, HS, VS encoded within the
serial data stream). In 18–bit color applications, the three video control signals maybe sent encoded within the
serial bit stream (restrictions apply) along with six additional general purpose signals.
Block Diagrams for the chipset are shown at the beginning of this datasheet.
Data Transfer
The DS92LV2411 / DS92LV2412 chipset will transmit and receive a pixel of data in the following format: C1 and
C0 represent the embedded clock in the serial stream. C1 is always HIGH and C0 is always LOW. The
remaining 26 bit spaces contain the scrambled, encoded and DC-Balanced serial data.
SER & DES OPERATING MODES AND REVERSE COMPATIBILITY (CONFIG[1:0])
The DS92LV2411 / DS92LV2412 chipset is compatible with other single serial lane Channel Link II or FPD-Link II
devices. Configuraiton modes are provided for reverse compatibility with the DS90C241 / DS90C124 and also
the DS90UR241 / DS90UR124 by setting the respective mode with the CONFIG[1:0] pins on the Ser or Des as
shown in Table and Table. This selection also determines whether the Control Signal Filter feature is enabled or
disabled in the Normal mode. These configuration modes are selectable the control pins only.
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