Datasheet

DS92LV2411, DS92LV2412
SNLS302C –MAY 2010–REVISED APRIL 2013 www.ti.com
Table 1. DS92LV2411 Ser Modes
CONFIG1 CONFIG0 MODE DES DEVICE
L L Normal Mode, Control Signal DS92LV2412, DS92LV2412,
Filter disabled DS92LV0422, DS92LV0412
L H Normal Mode, Control Signal DS92LV2412, DS92LV2412,
Filter enabled DS92LV0422, DS92LV0412
H L Reverse Compatibility Mode DS90UR124, DS99R124
H H Reverse Compatibility Mode DS90C124
Table 2. DS92LV2412 Des Modes
CONFIG1 CONFIG0 MODE SER DEVICE
L L Normal Mode, Control Signal DS92LV2411, DS92LV2411,
Filter disabled DS92LV0421, DS92LV0411
L H Normal Mode, Control Signal DS92LV2411, DS92LV2411,
Filter enabled DS92LV0421, DS92LV0411
H L Reverse Compatibility Mode DS90UR241
H H Reverse Compatibility Mode DS90C241
VIDEO CONTROL SIGNAL FILTER — SER & DES
When operating the devices in Normal Mode, the Control Signals have the following restrictions:
• Normal Mode with Control Signal Filter Enabled: Control Signal 1 and Control Signal 2 — Only 2 transitions
per 130 clock cycles are transmitted, the transition pulse must be 3 parallel clocks or longer.
• Normal Mode with Control Signal Filter Disabled: Control Signal 1 and Control Signal 2 — Only 2 transitions
per 130 clock cycles are transmitted, no restriction on minimum transition pulse.
• Control Signal 3 — Only 1 transition per 130 clock cycles is transmitted , minimum pulse width is 130 clock
cycles.
Control Signals are defined as low frequency signals with limited transition. Glitches of a control signal can cause
a visual error in display applications. This feature allows for the chipset to validate and filter out any high
frequency noise on the control signals. See Figure.
SERIALIZER Functional Description
The Ser converts a wide parallel input bus to a single serial output data stream, and also acts as a signal
generator for the chipset Built In Self Test (BIST) mode. The device can be configured via external pins or
through the optional serial control bus. The Ser features enhance signal quality on the link by supporting: a
selectable VOD level, a selectable de-emphasis signal conditioning and also the Channel Link II data coding that
provides randomization, scrambling, and DC Balanacing of the data. The Ser includes multiple features to reduce
EMI associated with display data transmission. This includes the randomization and scrambling of the data and
also the system spread spectrum clock support. The Ser features power saving features with a sleep mode, auto
stop clock feature, and optional LVCMOS (1.8 V) parallel bus compatibility.
See also the Functional Description of the chipset's serial control bus and BIST modes.
EMI Reduction Features
Data Randomization & Scrambling
Channel Link II Ser / Des feature a 3 step encoding process which enables the use of AC coupled interconnects
and also helps to manage EMI. The serializer first passes the parallel data through a scrambler which
randomizes the data. The randomized data is then DC balanced. The DC balanced and randomized data then
goes through a bit shuffling circuit and is transmitted out on the serial line. This encoding process helps to
prevent static data patterns on the serial stream. The resulting frequency content of the serial stream ranges
from the parallel clock frequency to the nyquist rate. For example, if the Ser / Des chip set is operating at a
parallel clock frequency of 50 MHz, the resulting frequency content of serial stream ranges from 50 MHz to 700
MHz ( 50 MHz *28 bits = 1.4 Gbps / 2 = 700 MHz ).
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