Datasheet

active serial stream X
PDB
(DES)
RIN
(Diff.)
LOCK
DO[23:0],
CO1,CO2,CO3
CLKOUT*
(DES)
PASS
OFF
OFF
Active ActiveLocking
L
H
L
H
Z
Z
L
L
Z
L
Z
CONDITIONS: * RFB = L, OSS_SEL = H , and OSC_SEL not equal to 000.
f
C0 or C1 Error
In Bit Stream
(Loss of LOCK)
Z
H
L
L
f
Z
H
Z
Z
DS92LV2411, DS92LV2412
www.ti.com SNLS302C –MAY 2010–REVISED APRIL 2013
Table 10. OSC_SEL (Oscillator) Configuration (continued)
OSC_SEL[2:0] INPUTS
CLKOUT Oscillator Frequency
OSC_SEL2 OSC_SEL1 OSC_SEL0
H L H 10 MHz ±40%
H H L 8.3 MHz ±40%
H H H 6.3 MHz ±40%
Figure 28. Des Outputs with Output State High and CLK Output Oscillator Option Enabled
Des — OP_LOW — Optional
The OP_LOW feature is used to hold the LVCMOS outputs, except for the LOCK output, at a LOW state. When
the OP_LOW feature is enabled, the LVCMOS outputs will be held at logic LOW while LOCK = LOW. The user
must toggle the OP_LOW Set/Reset register bit to release the outputs to the normal toggling state. Note that the
release of the outputs can only occur when LOCK is HIGH. The OP_LOW strap option is assigned to the PASS
pin, at pin location 42.
Restrictions on other straps:
1. Other strap options should not be used in order to keep the data and clock outputs at a true logic LOW state.
Other features should be selected through the I2C register interface.
2. The OSS_SEL feature is not available when OP_LOW is enabled.
Outputs DO[23:0], CO[3:1] and CLKOUT are in TRI-STATE before PDB toggles HIGH because the OP-LOW
strap value has not been recognized until the DS92LV2412 powers up. Figure 29 shows the user controlled
release of the OP_LOW and automatic reset of OP_LOW set on the falling edge of LOCK. Figure 30 shows the
user controlled release of OP_LOW and manual reset of OP_LOW set. Note manual reset of OP_LOW can only
occur when LOCK is HIGH.
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