Datasheet
37
38
39
40
41
42
43
44
45
46
47
48
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
36
35
34
33
32
31
30
29
28
27
26
25
DS92LV2411
TOP VIEW
DAP = GND
DI21
DI20
DI18
DI17
DI14
DI13
DI11
DI10
CONFIG[1]
VDDP
RES1
VDDHS
DOUT+
PDB
De-Emph
VODSEL
DI12
DI15
DI16
DI19 RES0
RES2
DOUT-
VDDTX
DI22
CI2
CLKIN
CONFIG[0]
DI23
DI8
DI7
DI6
DI5
BISTEN
VDDIO
DI4
DI3
DI2
DI1
DI9
VDDL
SCL
RFB
DI0
SDA
CI3
CI1
ID[x]
DS92LV2411, DS92LV2412
www.ti.com
SNLS302C –MAY 2010–REVISED APRIL 2013
DS92LV2411 Pin Diagram
Figure 4. Serializer - DS92LV2411 — Top View
DS92LV2411 Serializer PIN DESCRIPTIONS
(1)
Pin Name Pin # I/O, Type Description
LVCMOS Parallel Interface
DI[7:0] 34, 33, 32, 29, I, LVCMOS Parallel Interface Data Input Pins
28, 27, 26, 25 w/ pull-down For 8–bit RED Display: DI7 = R7 – MSB, DI0 = R0 – LSB.
DI[15:8] 42, 41, 40, 39, I, LVCMOS Parallel Interface Data Input Pins
38, 37, 36, 35 w/ pull-down For 8–bit GREEN Display: DI15 = G7 – MSB, DI8 = G0 – LSB.
DI[23:16] 2, 1, 48, 47, I, LVCMOS Parallel Interface Data Input Pins
46, 45, 44, 43 w/ pull-down For 8–bit BLUE Display: DI23 = B7 – MSB, DI16 = B0 – LSB.
CI1 5 I, LVCMOS Control Signal Input
w/ pull-down For Display/Video Application:
CI1 = Data Enable Input
Control signal pulse width must be 3 clocks or longer to be transmitted when the Control
Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition
pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00).
The signal is limited to 2 transitions per 130 clocks regardless of the Control Signal Filter
setting.
(1) NOTE: 1 = HIGH, 0 = LOW
The VDD (V
DDn
and V
DDIO
) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor on
the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
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