Datasheet

DS92LV2411, DS92LV2412
SNLS302C –MAY 2010–REVISED APRIL 2013 www.ti.com
DS92LV2411 Serializer PIN DESCRIPTIONS
(1)
(continued)
Pin Name Pin # I/O, Type Description
CI2 3 I, LVCMOS Control Signal Input
w/ pull-down For Display/Video Application:
CI2 = Horizontal Sync Input
Control signal pulse width must be 3 clocks or longer to be transmitted when the Control
Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition
pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00).
The signal is limited to 2 transitions per 130 clocks regardless of the Control Signal Filter
setting.
CI3 4 I, LVCMOS Control Signal Input
w/ pull-down For Display/Video Application:
CI3 = Vertical Sync Input
CI3 is limited to 1 transition per 130 clock cycles. Thus, the minimum pulse width allowed is
130 clock cycle wide.
CLKIN 10 I, LVCMOS Clock Input
w/ pull-down Latch/data strobe edge set by RFB pin.
Control and Configuration
PDB 21 I, LVCMOS Power-down Mode Input
w/ pull-down PDB = 1, Ser is enabled (normal operation).
Refer to ”Power Up Requirements and PDB Pin” in the Applications Information Section.
PDB = 0, Ser is powered down
When the Ser is in the power-down state, the driver outputs (DOUT+/-) are both logic high,
the PLL is shutdown, IDD is minimized. Control Registers are RESET.
VODSEL 24 I, LVCMOS Differential Driver Output Voltage Select
w/ pull-down VODSEL = 1, CML VOD is ±420 mV, 840 mVp-p (typ) — long cable / De-Emph applications
VODSEL = 0, CML VOD is ±280 mV, 560 mVp-p (typ) — short cable (no De-emph), low
power mode.
This is can also be control by I2C register.
De-Emph 23 I, Analog De-Emphasis Control
w/ pull-up De-Emph = open (float) - disabled
To enable De-emphasis, tie a resistor from this pin to GND or control via register.
See Table 4.
This can also be controlled by I2C register access.
RFB 11 I, LVCMOS Clock Input Latch/Data Strobe Edge Select
w/ pull-down RFB = 1, parallel interface data and control signals are latched on the rising clock edge.
RFB = 0, parallel interface data and control signals are latched on the falling clock edge.
This can also be controlled by I2C register access.
CONFIG[1: 13, 12 I, LVCMOS 00: Control Signal Filter DISABLED. Interfaces with DS92LV2412 or DS92LV0412
0] w/ pull-down 01: Control Signal Filter ENABLED. Interfaces with DS92LV2412 or DS92LV0412
10: Reverse compatibility mode to interface with the DS90UR124 or DS99R124Q
11: Reverse compatibility mode to interface with the DS90C124
ID[x] 6 I, Analog I2C Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 11.
SCL 8 I, LVCMOS I2C Serial Control Bus Clock Input - Optional
Open Drain SCL requires an external pull-up resistor to 3.3V.
SDA 9 I/O, LVCMOS I2C Serial Control Bus Data Input / Output - Optional
Open Drain SDA requires an external pull-up resistor 3.3V.
BISTEN 31 I, LVCMOS BIST Mode — Optional
w/ pull-down BISTEN = 0, BIST is disabled (normal operation)
BISTEN = 1, BIST is enabled
RES[2:0] 18, 16, 15 I, LVCMOS Reserved - tie LOW
w/ pull-down
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