Datasheet

DS92LV2411, DS92LV2412

www.ti.com

SNLS302C –MAY 2010–REVISED APRIL 2013

DS92LV2412 Deserializer PIN DESCRIPTIONS

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Pin Name Pin # I/O, Type Description

NC 1, 15, 16, Not Connected

30, 31, 45, Leave pin open (float)

46, 60

Channel-Link II — CML Serial Interface

RIN+ 49 I, CML True Input. The input must be AC Coupled with a 0.1 μF capacitor.

RIN- 50 I, CML Inverting Input. The input must be AC Coupled with a 0.1 μF capacitor.

CMF 51 I, Analog Common-Mode Filter

VCM center-tap is a virtual ground which may be ac-coupled to ground to increase receiver

common mode noise immunity. Recommended value is 4.7 μF or higher.

ROUT+ 52 O, CML True Output — Receive Signal after the Equalizer

NC if not used or connect to test point for monitor. Requires I2C control to enable.

ROUT- 53 O, CML Inverting Output — Receive Signal after the Equalizer

NC if not used or connect to test point for monitor. Requires I2C control to enable.

Power and Ground

Power must be supplied to all power pins for normal operation

VDDL 29 Power Logic Power, 1.8 V ±5%

VDDIR 48 Power Input Power, 1.8 V ±5%

VDDR 43, 55 Power RX High Speed Logic Power, 1.8 V ±5%

VDDSC 4, 58 Power SSCG Power, 1.8 V ±5%

VDDPR 57 Power PLL Power, 1.8 V ±5%

VDDCMLO 54 Power RX High Speed Logic Power, 1.8 V ±5%

VDDIO 13, 24, 38 Power LVCMOS I/O Power, 1.8 V ±5% OR 3.3 V ±10% (V

DDIO

)

GND DAP Ground DAP is the large metal contact at the bottom side, located at the center of the WQFN

package. Connected to the ground plane (GND) with at least 9 vias.

Product Folder Links: DS92LV2411 DS92LV2412