Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - serialisers Channel Link II (CML) WQFN 48

DS92LV2421, DS92LV2422

www.ti.com

SNLS321B –MAY 2010–REVISED APRIL 2013

DS92LV2421/DS92LV2422 10 to 75 MHz, 24-bit Channel Link II Serializer and Deserializer

Check for Samples: DS92LV2421, DS92LV2422

FEATURES

DESCRIPTION

The DS92LV2421 (Serializer) / DS92LV2422

• General

(Deserializer) chipset translates a parallel 24–bit

– 24–Bit Data, 3–Bit Control, 10 – 75 MHz

LVCMOS data interface into a single high-speed CML

Clock

serial interface with embedded clock information. This

– AC Coupled STP Interconnect Cable up to

single serial stream eliminates skew issues between

clock and data, reduces connector size and

10 Meters

interconnect cost for transferring a 24-bit or less, bus

– Integrated Terminations on Ser and Des

over FR-4 printed circuit board backplanes, and

– AT-SPEED Link BIST Mode and Reporting

balanced cables.

In addition to the 24-bit data bus interface, the

– Optional I2C Compatible Serial Control Bus

DS92LV2421 and DS92LV2422 also features a 3-bit

– Power Down Mode Minimizes Power

control bus for slow speed signals. This allows

Dissipation

implementing video and display applications with up

to 24–bits per pixel (RGB).

– 1.8V or 3.3V Compatible LVCMOS I/O

Interface

Programmable transmit de-emphasis, receive

equalization, on-chip scrambling and DC balancing

– -40° to +85°C Temperature Range

enables longer distance transmission over lossy

– >8 kV HBM

cables and backplanes. The DS92LV2422

• SERIALIZER — DS92LV2421

automatically locks to incoming data without an

external reference clock or special sync patterns,

– Data Scrambler for Reduced EMI

providing easy “plug-and-go” operation. EMI is

– DC-Balance Encoder for AC Coupling

minimized by the use of low voltage differential

– Selectable Output VOD and Adjustable De-

signaling, receiver drive strength control, and spread

emphasis

spectrum clocking capability.

• DESERIALIZER — DS92LV2422

The DS92LV2421, DS92LV2422 chipset is

– FAST Random Data Lock; no Reference

programmable though an I2C interface as well as

Clock Required

through pins. A built-in AT-SPEED BIST feature

validates link integrity and may be used for system

– Adjustable Input Receiver Equalization

diagnostics.

– LOCK (Real Time Link Status) Reporting

The DS92LV2421 is offered in a 48-pin WQFN and

the DS92LV2422 is offered in a 60-pin WQFN

– EMI Minimization on Output Parallel Bus

package. Both devices operate over the full industrial

(SSCG)

temperature range of -40°C to +85°C.

– Output Slew Control (OS)

APPLICATIONS

• Embedded Video and Display

• Medical Imaging

• Factory Automation

• Office Automation — Printer, Scanner

• Security and Video Surveillance

• General Purpose Data Communication

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (50 pages)

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DS92LV2421, DS92LV2422 www.ti.com SNLS321B – MAY 2010 – REVISED APRIL 2013 DS92LV2421/DS92LV2422 10 to 75 MHz, 24-bit Channel Link II Serializer and Deserializer Check for Samples: DS92LV2421, DS92LV2422 FEATURES DESCRIPTION • The DS92LV2421 (Serializer) / DS92LV2422 (Deserializer) chipset translates a parallel 24–bit LVCMOS data interface into a single high-speed CML serial interface with embedded clock information.
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DS92LV2421, DS92LV2422 SNLS321B – MAY 2010 – REVISED APRIL 2013 www.ti.com Applications Diagram VDDIO VDDn (1.8V or 3.3V) 1.8V DI[7:0] DI[15:8] DI[23:16] CI1 CI2 CI3 CLKIN Graphic Processor OR Video Imager OR ASIC/FPGA PDB Channel Link II 1 Pair / AC Coupled 100 nF 100 nF DOUT+ RIN+ DOUT- RIN100 ohm STP Cable DS92LV2421 Serializer BISTEN Optional VDDn VDDIO 1.8V (1.8V or 3.
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DS92LV2421, DS92LV2422 www.ti.
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DS92LV2421, DS92LV2422 SNLS321B – MAY 2010 – REVISED APRIL 2013 www.ti.com DS92LV2421 Serializer Pin Descriptions Pin Name Pin # I/O, Type Description (1) LVCMOS Parallel Interface DI[7:0] 34, 33, 32, 29, 28, 27, 26, 25 I, LVCMOS Parallel Interface Data Input Pins w/ pullFor 8–bit RED Display: DI7 = R7 – MSB, DI0 = R0 – LSB. down DI[15:8] 42, 41, 40, 39, 38, 37, 36, 35 I, LVCMOS Parallel Interface Data Input Pins w/ pullFor 8–bit GREEN Display: DI15 = G7 – MSB, DI8 = G0 – LSB.
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DS92LV2421, DS92LV2422 www.ti.com SNLS321B – MAY 2010 – REVISED APRIL 2013 DS92LV2421 Serializer Pin Descriptions (continued) Pin Name Pin # BISTEN 31 RES[2:0] 18, 16, 15 I/O, Type Description (1) I, LVCMOS BIST Mode — Optional w/ pullBISTEN = 0, BIST is disabled (normal operation) down BISTEN = 1, BIST is enabled I, LVCMOS Reserved - tie LOW w/ pulldown Channel-Link II — CML Serial Interface DOUT+ 20 O, CML Non–Inverting Output. The output must be AC Coupled with a 0.1 µF capacitor.
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DS92LV2421, DS92LV2422 SNLS321B – MAY 2010 – REVISED APRIL 2013 www.ti.com DS92LV2422 Deserializer Pin Descriptions Pin Name Pin # I/O, Type Description (1) LVCMOS Parallel Interface DO[7:0] 33, 34, 35, 36, 37, 39, 40, 41 I, STRAP, O, LVCMOS Parallel Interface Data Output Pins For 8–bit RED Display: DO7 = R7 – MSB, DO0 = R0 – LSB. In power-down (PDB = 0), outputs are controlled by the OSS_SEL (See Table 8). These pins are inputs during power-up (See STRAP Inputs).
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DS92LV2421, DS92LV2422 www.ti.com SNLS321B – MAY 2010 – REVISED APRIL 2013 DS92LV2422 Deserializer Pin Descriptions (continued) Pin Name Description (1) Pin # I/O, Type OS_CLKOUT 11 [DO21] STRAP I, LVCMOS w/ pull-down Output CLKOUT Slew Select OS_CLKOUT = 1, Increased CLKOUT slew rate OS_CLKOUT = 0, Normal CLKOUT slew rate (default) This can also be controlled by I2C register access.
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DS92LV2421, DS92LV2422 SNLS321B – MAY 2010 – REVISED APRIL 2013 www.ti.com DS92LV2422 Deserializer Pin Descriptions (continued) Pin Name Pin # I/O, Type Description (1) Channel-Link II — CML Serial Interface RIN+ 49 I, CML True Input. The input must be AC Coupled with a 0.1 μF capacitor. RIN- 50 I, CML Inverting Input. The input must be AC Coupled with a 0.1 μF capacitor.
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DS92LV2421, DS92LV2422 www.ti.com SNLS321B – MAY 2010 – REVISED APRIL 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) −0.3V to +2.5V Supply Voltage – VDDn (1.8V) −0.3V to +4.0V Supply Voltage – VDDIO −0.3V to (VDDIO + 0.3V) LVCMOS I/O Voltage Receiver Input Voltage −0.3V to (VDD + 0.
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DS92LV2421, DS92LV2422 SNLS321B – MAY 2010 – REVISED APRIL 2013 www.ti.com Recommended Operating Conditions Min (1) Nom Max (1) Units Supply Voltage (VDDn) 1.71 1.8 1.89 V LVCMOS Supply Voltage (VDDIO) 1.71 1.8 1.89 V OR LVCMOS Supply Voltage (VDDIO) 3.0 3.3 3.6 V Operating Free Air Temperature (TA) −40 +25 +85 °C Clock Frequency 10 75 MHz 50 mVP-P Supply Noise (1) (2) (2) Specification is verified by design and is not tested in production.
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DS92LV2421, DS92LV2422 www.ti.com SNLS321B – MAY 2010 – REVISED APRIL 2013 Serializer DC Electrical Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3) Symbol RTO Parameter Conditions Pin/Freq.
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DS92LV2421, DS92LV2422 SNLS321B – MAY 2010 – REVISED APRIL 2013 www.ti.com Deserializer DC Electrical Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Pin/Freq. Min Max Units 1.23 5 VDDIO V PDB, BISTEN GND 0.595 V −15 ±1 +15 μA DO[23:0], CO1, CO2, CO3, CLKOUT, LOCK, PASS VDDI VDDIO (1) Typ (1) 1.8 V I/O LVCMOS DC SPECIFICATIONS – VDDIO = 1.71 to 1.
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DS92LV2421, DS92LV2422 www.ti.com SNLS321B – MAY 2010 – REVISED APRIL 2013 Deserializer DC Electrical Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter IDDZ Conditions PDB = 0V, All other LVCMOS Inputs = 0V Deserializer Supply Current Power Down Pin/Freq. VDD= 1.89V VDDIO =1.89 V IDDIOZ Min (1) All VDD pins Typ Max Units 100 3000 µA 6 50 µA 12 100 µA (1) VDDIO VDDIO = 3.
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DS92LV2421, DS92LV2422 SNLS321B – MAY 2010 – REVISED APRIL 2013 www.ti.com Serializer Switching Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol λSTXBW Parameter Serializer Jitter Transfer Function -3 dB Bandwidth δSTX Serializer Jitter Transfer Function Peaking Min (1) Conditions Typ Max (1) Units RL = 100Ω, De-Emph = disabled, RANDOM pattern, CLKIN = 75MHz 3.
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DS92LV2421, DS92LV2422 www.ti.com SNLS321B – MAY 2010 – REVISED APRIL 2013 Deserializer Switching Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol tDCCJ tIJT Parameter Des Cycle-to-Cycle Jitter Des Input Jitter Tolerance, Figure 18 Conditions SSC[3:0] = OFF Min (1) Pin/Freq.
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DS92LV2421, DS92LV2422 SNLS321B – MAY 2010 – REVISED APRIL 2013 www.ti.com DC and AC Serial Control Bus Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Min (1) Conditions Typ Max (1) Units V VIH Input High Level SDA and SCL 2.2 VDD 3.3V VIL Input Low Level Voltage SDA and SCL GND 0.
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DS92LV2421, DS92LV2422 www.ti.com SNLS321B – MAY 2010 – REVISED APRIL 2013 +VOD 80% (DOUT+) - (DOUT-) 0V 20% -VOD tLLHT tLHLT Figure 5. Serializer Output Transition Times tTCIH tTCP CLKIN w/ RFB = L tTCIL 80% 20% 1/2 VDDIO tCLKT tDIS GND tCLKT VDDIO VIHmin VILmax DI[23:0], CI1,CI2,CI3 VDDIO GND tDIH Figure 6. Serializer Input CLKIN Waveform and Set and Hold Times PDB CLKIN 1/2 VDDIO "X" active tPLD DOUT (Diff.) Driver OFF, VOD = 0V Driver On Figure 7.
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DS92LV2421, DS92LV2422 SNLS321B – MAY 2010 – REVISED APRIL 2013 1/2 VDDIO PDB CLKIN www.ti.com active "X" tXZD DOUT (Diff.) active Driver OFF, VOD = 0V Figure 8. Serializer Disable Time DIN[23:0], CI1,CI2,CI3 SYMBOL N SYMBOL N+1 tSD CLKIN (RFB = L) START BIT STOP START BIT BIT STOP BIT DOUT (Diff.) SYMBOL N-1 SYMBOL N Figure 9. Serializer Latency Delay tDJIT tDJIT VOD (+) DOUT (Diff.) TxOUT_E_O 0V VOD (-) tBIT (1 UI) Figure 10.
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DS92LV2421, DS92LV2422 www.ti.com SNLS321B – MAY 2010 – REVISED APRIL 2013 VDDIO 80% 20% GND tCLH tCHL Figure 12. Deserializer LVCMOS Transition Times START BIT STOP START BIT BIT STOP BIT RIN (Diff.) SYMBOL N SYMBOL N+1 tDD CLKOUT (RFB = L) DO[23:0], CO1,CO2,CO3 SYMBOL N-2 SYMBOL N-1 SYMBOL N Figure 13. Deserializer Delay – Latency 1/2 VDDIO PDB RIN (Diff.) active "X" tXZR CLKOUT, DO[23:0], CO1,CO2,CO3 PASS, LOCK active Z (TRI-STATE) Figure 14.
PAGE 20
DS92LV2421, DS92LV2422 SNLS321B – MAY 2010 – REVISED APRIL 2013 PDB www.ti.com 2.0V 0.8V RIN (Diff.) 'RQ¶W &DUH tDDLT LOCK TRI-STATE or LOW Z or L tRxZ DO[23:0], CO1,CO2,CO3 TRI-STATE or LOW or Pulled Up CLKOUT (RFB = L) Z or L or PU TRI-STATE or LOW OFF IN LOCK TIME Z or L ACTIVE OFF Figure 15. Deserializer PLL Lock Times and PDB TRI-STATE Delay VDDIO CLKOUT w/ RFB = H 1/2 VDDIO GND DO[23:0], CO1,CO2,CO3 VDDIO 1/2 VDDIO 1/2 VDDIO GND tROS tROH Figure 16.
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DS92LV2421, DS92LV2422 www.ti.com SNLS321B – MAY 2010 – REVISED APRIL 2013 Ideal Data Bit End Sampling Window Ideal Data Bit Beginning RxIN_TOL Left VTH 0V VTL RxIN_TOL Right Ideal Center Position (tBIT/2) tBIT (1 UI) tRJIT = RxIN_TOL (Left + Right) - tRJIT Sampling Window = 1 UI Figure 18. Receiver Input Jitter Tolerance BISTEN 1/2 VDDIO tPASS PASS (w/ errors) 1/2 VDDIO Current BIST Test - Toggle on Error Prior BIST Result Result Held Figure 19.
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DS92LV2421, DS92LV2422 SNLS321B – MAY 2010 – REVISED APRIL 2013 www.ti.com FUNCTIONAL DESCRIPTION The DS92LV2421 / DS92LV2422 chipset transmits and receives 24-bits of data and 3 control signals over a single serial CML pair operating at 280 Mbps to 2.1 Gbps. The serial stream also contains an embedded clock, video control signals and the DC-balance information which enhances signal quality and supports AC coupling.
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DS92LV2421, DS92LV2422 www.ti.com SNLS321B – MAY 2010 – REVISED APRIL 2013 cycles. Control Signals are defined as low frequency signals with limited transition. Glitches of a control signal can cause a visual error in display applications. This feature allows for the chipset to validate and filter out any high frequency noise on the control signals. See Figure.
PAGE 24
DS92LV2421, DS92LV2422 SNLS321B – MAY 2010 – REVISED APRIL 2013 www.ti.com Ser — De-Emphasis (De-Emph) The De-Emph pin controls the amount of de-emphasis beginning one full bit time after a logic transition that the Ser drives. This is useful to counteract loading effects of long or lossy cables. This pin should be left open for standard switching currents (no de-emphasis) or if controlled by register. De-emphasis is selected by connecting a resistor on this pin to ground, with R value between 0.
PAGE 25
DS92LV2421, DS92LV2422 www.ti.com SNLS321B – MAY 2010 – REVISED APRIL 2013 Ser — Pixel Clock Edge Select (RFB) The RFB pin determines the edge that the data is latched on. If RFB is High, input data is latched on the Rising edge of the CLKIN. If RFB is Low, input data is latched on the Falling edge of the CLKIN. Ser and Des maybe set differently. This feature may be controlled by the external pin or by register.
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DS92LV2421, DS92LV2422 SNLS321B – MAY 2010 – REVISED APRIL 2013 www.ti.com Des — Common Mode Filter Pin (CMF) — Optional The Des provides access to the center tap of the internal termination. A capacitor may be placed on this pin for additional common-mode filtering of the differential pair. This can be useful in high noise environments for additional noise rejection capability. A 4.7 µF capacitor may be connected to this pin to Ground.
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DS92LV2421, DS92LV2422 www.ti.com SNLS321B – MAY 2010 – REVISED APRIL 2013 Table 7. SSCG Configuration (LF_MODE = H) — Des Output SSC[3:0] Inputs LH_MODE = H (10 - 20 MHz) Result SSC3 SSC2 SSC1 SSC0 fdev (%) fmod (kHz) L L L L L L L NA Disable H ±0.5 L L H L ±1.0 L L H H ±1.5 L H L L ±2.0 L H L H ±0.5 L H H L ±1.0 L H H H ±1.5 H L L L ±2.0 H L L H ±0.5 H L H L ±1.0 H L H H ±1.5 H H L L ±2.0 H H L H ±0.5 H H H L ±1.
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DS92LV2421, DS92LV2422 SNLS321B – MAY 2010 – REVISED APRIL 2013 www.ti.com Des — Oscillator Output — Optional The Des provides an optional clock output when the input clock (serial stream) has been lost. This is based on an internal oscillator. The frequency of the oscillator may be selected. This feature may be controlled by the external pin or by register. See Table 9 and Table 10. Table 8.
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DS92LV2421, DS92LV2422 www.ti.com SNLS321B – MAY 2010 – REVISED APRIL 2013 PDB (DES) RIN (Diff.) active serial stream X H LOCK H L L L DO[23:0], CO1,CO2,CO3 L L L CLKOUT* (DES) L L L PASS H Locking OFF C0 or C1 Error In Bit Stream (Loss of LOCK) Active Active OFF CONDITIONS: * RFB = L, and OSS_SEL = H Figure 24. Des Outputs with Output State Select High (OSS_SEL = H) Table 10.
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DS92LV2421, DS92LV2422 SNLS321B – MAY 2010 – REVISED APRIL 2013 www.ti.com Des — OP_LOW — Optional The OP_LOW feature is used to hold the LVCMOS outputs, except for the LOCK output, at a LOW state. When the OP_LOW feature is enabled, the LVCMOS outputs will be held at logic LOW while LOCK = LOW. The user must toggle the OP_LOW Set/Reset register bit to release the outputs to the normal toggling state. Note that the release of the outputs can only occur when LOCK is HIGH.
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DS92LV2421, DS92LV2422 www.ti.com SNLS321B – MAY 2010 – REVISED APRIL 2013 2.0V PDB LOCK OP_LOW SET (Strap pin) User controlled User controlled OP_ LOW RELEASE/SET (Register) DO[23:0], CO3, CO2, CO1 TRISTATE ACTIVE CLKOUT TRISTATE ACTIVE Figure 27. OP_LOW Manual Set/Reset Des — Clock Edge Select (RFB) The RFB pin determines the edge that the data is strobed on. If RFB is High, output data is strobed on the Rising edge of the CLKOUT.
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DS92LV2421, DS92LV2422 SNLS321B – MAY 2010 – REVISED APRIL 2013 www.ti.com Built In Self Test (BIST) An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high-speed serial link. This is useful in the prototype stage, equipment production, in-system test and also for system diagnostics. In the BIST mode only a input clock is required along with control to the Ser and Des BISTEN input pins. The Ser outputs a test pattern (PRBS7) and drives the link at speed.
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DS92LV2421, DS92LV2422 www.ti.com SNLS321B – MAY 2010 – REVISED APRIL 2013 BER Calculations It • • • is possible to calculate the approximate Bit Error Rate (BER). The following is required: Clock Frequency (MHz) BIST Duration (seconds) BIST test Result (PASS) The BER is less than or equal to one over the product of 24 times the CLK rate times the test duration. If we assume a 65 MHz clock, a 10 minute (600 second) test, and a PASS, the BERT is ≤ 1.
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DS92LV2421, DS92LV2422 SNLS321B – MAY 2010 – REVISED APRIL 2013 www.ti.com 1.8V 10 k VDDIO ID[X] 4.7k HOST 4.7k RID SCL SCL SDA SDA SER or DES To other Devices Figure 30. Serial Control Bus Connection The third pin is the ID[X] pin. This pin sets one of five possible device addresses. Three different connections are possible. The pin may be tied to ground. The pin may be pulled to VDD (1.8V, NOT VDDIO)) with a 10 kΩ resistor. Or a 10 kΩ pull up resistor (to VDD1.
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DS92LV2421, DS92LV2422 www.ti.com SNLS321B – MAY 2010 – REVISED APRIL 2013 Table 12. ID[x] Resistor Value – DS92LV2422 Des Resistor RID kΩ Address 7'b Address 8'b 0 appended (WRITE) 0.47 7b' 111 0001 (h'71) 8b' 1110 0010 (h'E2) 2.7 7b' 111 0010 (h'72) 8b' 1110 0100 (h'E4) 8.
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DS92LV2421, DS92LV2422 SNLS321B – MAY 2010 – REVISED APRIL 2013 www.ti.com Table 13. SERIALIZER — Serial Bus Control Registers (continued) ADD ADD Register (dec) (hex) Name 2 2 De-Emphasis Control Bit(s) R/W Default (bin) Function Description 7:5 R/W 000 De-E Setting 000: 001: 010: 011: 100: 101: 110: 111: 4 R/W 0 De-E EN 0: De-Emphasis Enabled 1: De-Emphasis Disabled 3:0 R/W 000 Reserved Reserved set by external Resistor -1 dB -2 dB -3.3 dB -5 dB -6.7 dB -9 dB -12 dB Table 14.
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DS92LV2421, DS92LV2422 www.ti.com SNLS321B – MAY 2010 – REVISED APRIL 2013 Table 14.
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DS92LV2421, DS92LV2422 SNLS321B – MAY 2010 – REVISED APRIL 2013 www.ti.com Table 14.
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DS92LV2421, DS92LV2422 www.ti.com SNLS321B – MAY 2010 – REVISED APRIL 2013 DS92LV2421 (SER) VDDIO VDDIO C9 C7 FB1 C3 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DI9 DI10 DI11 DI12 DI13 DI14 DI15 LVCMOS Parallel Video Interface VDDTX VDDHS CI1 CI2 CI3 LVCMOS Control Interface BISTEN PDB C12 CONFIG1 CONFIG0 RFB C4 FB2 C5 FB3 C6 FB4 C8 C10 VDDP C11 VDDL C1 Serial Channel Link II Interface DOUT+ DOUTC2 DI16 DI17 DI18 DI19 DI20 DI21 DI22 DI23 CLKIN 1.8V VDDIO VODSEL De-Emph 1.
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DS92LV2421, DS92LV2422 SNLS321B – MAY 2010 – REVISED APRIL 2013 www.ti.com DS92LV2422 (DES) 1.8V VDDL C13 C11 VDDIO VDDIO C8 C3 VDDSC C12 C14 VDDIO C9 C4 VDDPR VDDIO C10 C5 VDDR C15 C6 VDDIR VDDIO EXAMPLE: STRAP Input Pull-Ups (10k) VDDCMLO C16 C7 C1 Serial Channel Link II Interface RIN+ RINCMF C2 C17 TP_A ROUT+ ROUT- TP_B Host Control BISTEN PDB C18 1.8V 10k ID[X] SCL SDA RID C1 - C2 = 0.1 PF (50 WV) C3 - C12 = 0.1 PF C13, C16 = 4.
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DS92LV2421, DS92LV2422 www.ti.com SNLS321B – MAY 2010 – REVISED APRIL 2013 TRANSMISSION MEDIA The Ser/Des chipset is intended to be used in a point-to-point configuration, through a PCB trace, or through twisted pair cable. The Ser and Des provide internal terminations providing a clean signaling environment. The interconnect for LVDS should present a differential impedance of 100 Ohms. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities.
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DS92LV2421, DS92LV2422 SNLS321B – MAY 2010 – REVISED APRIL 2013 www.ti.com LVDS INTERCONNECT GUIDELINES See AN-1108(SNLA008) and AN-905(SNLA035) for full details.
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DS92LV2421, DS92LV2422 www.ti.com SNLS321B – MAY 2010 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision A (April 2013) to Revision B • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 16-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing DS92LV2421SQ/NOPB WQFN RHS 48 DS92LV2421SQE/NOPB WQFN RHS DS92LV2421SQX/NOPB WQFN RHS DS92LV2422SQ/NOPB WQFN DS92LV2422SQE/NOPB DS92LV2422SQX/NOPB SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS92LV2421SQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 DS92LV2421SQE/NOPB WQFN RHS 48 250 213.0 191.0 55.0 DS92LV2421SQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 DS92LV2422SQ/NOPB WQFN NKB 60 1000 367.0 367.0 38.0 DS92LV2422SQE/NOPB WQFN NKB 60 250 213.0 191.0 55.
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MECHANICAL DATA NKB0060B SQA60B (Rev B) www.ti.
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