Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - serialisers Channel Link III (CML) WQFN 32

DS92LX1621, DS92LX1622

www.ti.com

SNLS327I –MAY 2010–REVISED JANUARY 2014

DS92LX1621/DS92LX1622 10 - 50 MHz DC-Balanced Channel Link III Serializer and

Deserializer with Bi-Directional Control Channel

Check for Samples: DS92LX1621, DS92LX1622

FEATURES

• SER Package: 32 Pin WQFN (5mm x 5mm)

• DES Package: 40 Pin WQFN (6mm x 6mm)

• Configurable Data Throughput

– 12–bit (min) up to 600 Mbits/sec

APPLICATIONS

– 16–bit (def) up to 800 Mbits/sec

• Industrial Displays, Touch Screens

– 18–bit (max) up to 900 Mbits/sec

• Medical Imaging

• 10 MHz to 50 MHz Input Clock Support

• Embedded Clock with DC Balanced Coding to

DESCRIPTION

Support AC-Coupled Interconnects

The DS92LX1621 / DS92LX1622 chipset offers a

• Capable to Drive up to 10 Meters Shielded

Channel Link III interface with a high-speed forward

Twisted-Pair

channel and a full-duplex back channel for data

transmission over a single differential pair. The

• Bi-Directional Control Interface Channel with

Serializer/Deserializer pair is targeted for direct

C Support

connections between automotive camera systems

• I

C Interface for Device Configuration. Single-

and Host Controller/Electronic Control Unit (ECU).

pin ID Addressing

The primary transport sends 16 bits of image data

• 16–bit Data Payload with CRC (Cyclic

over a single high-speed serial stream together with a

low latency bi-directional control channel transport

Redundancy Check) for Checking Data

that supports I

C. Included with the 16-bit payload is

Integrity with Programmable Data

a selectable data integrity option for CRC (Cyclic

Transmission Error Detection and Interrupt

Redundancy Check) or parity bit to monitor

Control

transmission link errors. Using TI’s embedded clock

• Up to 6 Programmable GPIO's

technology allows transparent full-duplex

• AT-SPEED BIST Diagnosis Feature to Validate

communication over a single differential pair, carrying

asymmetrical bi-directional control information without

Link Integrity

the dependency of video blanking intervals. This

• Individual Power-Down Controls for Both SER

single serial stream simplifies transferring a wide data

and DES

bus over PCB traces and cable by eliminating the

• User-Selectable Clock Edge for Parallel Data

skew problems between parallel data and clock

on Both SER and DES

paths. This significantly saves system cost by

narrowing data paths that in turn reduce PCB layers,

• Integrated Termination Resistors

cable width, and connector size and pins.

• 1.8V- or 3.3V-Compatible Parallel Bus Interface

In addition, the Deserializer inputs provide

• Single Power Supply at 1.8V

equalization control to compensate for loss from the

• IEC 61000–4–2 ESD Compliant

media over longer distances. Internal DC balanced

• No Reference Clock Required on Deserializer

encoding/decoding is used to support AC-Coupled

interconnects.

• Programmable Receive Equalization

• LOCK Output Reporting Pin to Ensure Link

The sleep function provides a power-savings mode

Status

and a remote wake up interrupt for signaling of a

remote device.

• EMI/EMC Mitigation

The Serializer is offered in a 32-pin WQFN package,

– DES Programmable Spread Spectrum

and Deserializer is offered in a 40-pin WQFN

(SSCG) Outputs

package.

– DES Receiver Staggered Outputs

• Temperature Range −40°C to +85°C

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (47 pages)

PAGE 1
DS92LX1621, DS92LX1622 www.ti.
PAGE 2
DS92LX1621, DS92LX1622 SNLS327I – MAY 2010 – REVISED JANUARY 2014 www.ti.com Typical Application Diagram Parallel Data In 16 Image Sensor Parallel Data Out 16 Channel Link III 2 2 DS92LX1622 DS92LX1621 Bidirectional Back Ch. Cntl Bus Serializer Microcontroller/ ECU Bidirectional Back Ch. Cntl Bus Bi-direction Back Channel Deserializer Figure 1.
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DS92LX1621, DS92LX1622 www.ti.
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DS92LX1621, DS92LX1622 SNLS327I – MAY 2010 – REVISED JANUARY 2014 www.ti.com DS92LX1621 Serializer PIN DESCRIPTIONS (continued) Pin Name Pin No. I/O, Type Description SERIAL CONTROL BUS - I2C COMPATIBLE SCL 4 Input/Output, Digital Clock line for the serial control bus communication SCL requires an external pull-up resistor to VDDIO. SDA 5 Input/Output, Open Drain Data line for the serial control bus communication SDA requires an external pull-up resistor to VDDIO.
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DS92LX1621, DS92LX1622 www.ti.
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DS92LX1621, DS92LX1622 SNLS327I – MAY 2010 – REVISED JANUARY 2014 www.ti.com DS92LX1622 Deserializer PIN DESCRIPTIONS (continued) Pin Name Pin No. I/O, Type 2 Input/Output, Open Drain 40 Input, LVCMOS w/ pull up SDA Description Data line for serial control bus communication SDA requires an external pull-up resistor to VDDIO.
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DS92LX1621, DS92LX1622 www.ti.com SNLS327I – MAY 2010 – REVISED JANUARY 2014 Absolute Maximum Ratings (1) (2) −0.3V to +2.5V Supply Voltage ( VDD1V8) −0.3V to +4.0V Supply Voltage (VDD3V3) LVCMOS Input Voltage (VDD1V8) −0.3V to +(VDD1V8 + 0.3V) LVCMOS Input Voltage (VDD3V3) −0.3V to +(VDD3V3 + 0.3V) −0.3V to +(VDD + 0.3V) LVCMOS Output Voltage (VDD) CML Driver I/O Voltage (VDD1V8) −0.3V to (VDD1V8 + 0.3V) CML Receiver I/O Voltage (VDD1V8) −0.3V to (VDD1V8 + 0.
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DS92LX1621, DS92LX1622 SNLS327I – MAY 2010 – REVISED JANUARY 2014 www.ti.com Serializer Electrical Characteristics (1) (2) (3) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit s LVCMOS DC SPECIFICATIONS 3.3V I/O (SER INPUTS, DES OUTPUTS, GPIO, CONTROL INPUTS AND OUTPUTS) VIH High Level Input Voltage VIN = 3.0V to 3.6V 2.0 VIN V VIL Low Level Input Voltage VIN = 3.0V to 3.6V GND 0.
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DS92LX1621, DS92LX1622 www.ti.com SNLS327I – MAY 2010 – REVISED JANUARY 2014 Serializer Electrical Characteristics(1)(2)(3) (continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit s VIN Differential Input Voltage Range RIN+ - RIN- 180 IIN Input Current VIN = VDD or 0V, VDD = 1.
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DS92LX1621, DS92LX1622 SNLS327I – MAY 2010 – REVISED JANUARY 2014 www.ti.com Recommended Serializer Timing for PCLK (1) (2) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter tTCP Transmit Clock Period tTCIH Transmit Clock Input High Time Conditions Typ Max Units 20 T 100 ns 0.4T 0.5T 0.6T ns 0.4T 0.5T 0.
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DS92LX1621, DS92LX1622 www.ti.com SNLS327I – MAY 2010 – REVISED JANUARY 2014 Deserializer Switching Characteristics (1) (2) (3) (4) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol tRCP Parameter Conditions Pin/Freq. Min Typ Max Units Receiver Output Clock Period tRCP = tTCP PCLK 20 T 100 ns tPDC PCLK Duty Cycle Default Registers SSCG[3:0] = OFF PCLK 45 50 55 % tCLH LVCMOS Low-to-High Transition Time 1.3 2.0 2.
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DS92LX1621, DS92LX1622 SNLS327I – MAY 2010 – REVISED JANUARY 2014 www.ti.com Bi-Directional Control Bus Timing Specifications (SCL, SDA) - (See Figure 6) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions RECOMMENDED INPUT TIMING REQUIREMENTS Min Typ Max Units 100 kHz (1) fSCL SCL Clock Frequency >0 fLOW SCL Low Period 4.7 µs fHIGH SCL High Period 4.0 µs tHD:STA Hold time for a start or a repeated start condition 4.
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DS92LX1621, DS92LX1622 www.ti.com SNLS327I – MAY 2010 – REVISED JANUARY 2014 SDA tLOW tf tHD;STA tr tf tBUF tr tSP SCL tSU;STA tHD;STA tHIGH tSU;STO tSU;DAT tHD;DAT START STOP REPEATED START START Figure 6. Bi-Directional Control Bus Timing Bi-Directional Control Bus DC Characteristics (SCL, SDA) - I2C Compliant Symbol Parameter Conditions Min Typ Max Units VIH Input High Level SDA and SCL 0.7 x VDDIO VDDIO V VIL Input Low Level Voltage SDA and SCL GND 0.
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DS92LX1621, DS92LX1622 SNLS327I – MAY 2010 – REVISED JANUARY 2014 www.ti.com 100 nF DOUT+ 50: ZDiff = 100: SCOPE BW 8 4.0 GHz 100: 50: DOUT- 100 nF 16 DIN/HS/VS PARALLEL-TO-SERIAL Figure 9. Serializer CML Output Load and Transition Times DOUT+ RL DOUT- PCLK Figure 10. Serializer VOD DC Diagram DOUT- Single Ended V V OD V OD+ ODV DOUT+ | OS 0V Differential V OD+ 0V (DOUT+)-(DOUT-) V OD- Figure 11. Serializer VOD DC Diagram RIN+ VCM = 1.
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DS92LX1621, DS92LX1622 www.ti.com SNLS327I – MAY 2010 – REVISED JANUARY 2014 80% VDD 80% PCLK 20% 20% 0V tCLKT tCLKT Figure 13. Serializer Input Clock Transition Times tTCP PCLK VDDIO/2 tDIS VDDIO/2 VDDIO/2 tDIH VDDIO DIN/HS/VS VDDIO/2 Setup Hold VDDIO/2 0V Figure 14. Serializer Setup/Hold Times PDB (3.3V I/O) 2.0V PCLK tPLD TRI-STATE DOUT± TRI-STATE Output Active DIN/HS/VS SYMBOL N SYMBOL N+1 SYMBOL N+2 SYMBOL N+3 | | Figure 15.
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DS92LX1621, DS92LX1622 SNLS327I – MAY 2010 – REVISED JANUARY 2014 www.ti.com 2.0V PDB (3.3V I/O) | | t DDLT RIN ± TRI - STATE | LOCK Figure 17. Deserializer Data Lock Time 80% 80% Deserializer 20% 8 pF lumped 20% tCLH tCHL Figure 18.
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DS92LX1621, DS92LX1622 www.ti.com SNLS327I – MAY 2010 – REVISED JANUARY 2014 Frequency FPCLK+ fdev fdev (max) FPCLK FPCLK- fdev (min) Time 1 / fmod Figure 21. Spread Spectrum Clock Output Profile 2 JITTER TRANSFER (dB) 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 1.0E+04 1.0E+05 1.0E+06 1.0E+07 MODULATION FREQUENCY (Hz) Figure 22. Typical Serializer Jitter Transfer Function at 43 MHz 0.62 JITTER AMPLITUDE (UI) 0.61 0.60 0.59 0.58 0.57 0.56 0.55 0.54 0.53 0.52 1.0E+04 1.0E+05 1.0E+06 1.
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DS92LX1621, DS92LX1622 SNLS327I – MAY 2010 – REVISED JANUARY 2014 www.ti.com Table 1. DS92LX1621 Control Registers Addr (Hex) 0 Name Bits Field R/W Default 7:1 DEVICE ID RW 0x58 SER ID RW 0 0: Device ID is from CAD 1: Register I2C Device ID overrides CAD 0 Reserved 7:3 2 Reserved 18 2 STANDBY RW 0 Standby mode control. Retains control register data. Supported only when M/S = 0 0: Enabled. Low-current Standby mode with wake-up capability. Suspends all clocks and functions.
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DS92LX1621, DS92LX1622 www.ti.com SNLS327I – MAY 2010 – REVISED JANUARY 2014 Table 1. DS92LX1621 Control Registers (continued) Addr (Hex) Name 5 I2C Bus Rate 6 DES ID Bits Field R/W Default Description 7:0 I2C BUS RATE RW 0x40 I2C ratio is determined by the following: fSCL = 6.25 MHz / register value (in decimal) 0x40'h = ~100 kHz SCL (default) Note: Register values <0x32'h are NOT supported.
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DS92LX1621, DS92LX1622 SNLS327I – MAY 2010 – REVISED JANUARY 2014 www.ti.com Table 1. DS92LX1621 Control Registers (continued) Addr (Hex) 12 13 Name GPIO[5] Config General Purpose Control Reg Bits Field 7:4 RESERVED 0 Reserved 3:2 RESERVED 0 Reserved 1 GPIO5 DIR RW 1 0: Output 1: Input 0 GPIO5 EN RW 1 0: TRI-STATE 1: Enabled GPCR[7] GPCR[6] GPCR[5] GPCR[4] GPCR[3] GPCR[2] GPCR[1] GPCR[0] RW 0 0: LOW 1: HIGH 7:0 R/W Default Description Table 2.
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DS92LX1621, DS92LX1622 www.ti.com SNLS327I – MAY 2010 – REVISED JANUARY 2014 Table 2. DS92LX1622 Control Registers (continued) Addr (Hex) Name Bits R/W Default Description 7 Tx CRC CHECK ENABLE RW 1 Back Channel CRC Enable 0: Disable 1: Enable For proper CRC operation, on Serailizer 0x03h b[6] control register must be Enabled. 6 Rx CRC GEN ENABLE RW 1 Foward Channel CRC Enable 0: Disable 1: Enable For proper CRC operation, on Serailizer 0x03h b[7] control register must be Enabled.
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DS92LX1621, DS92LX1622 SNLS327I – MAY 2010 – REVISED JANUARY 2014 www.ti.com Table 2.
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DS92LX1621, DS92LX1622 www.ti.com SNLS327I – MAY 2010 – REVISED JANUARY 2014 Table 2.
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DS92LX1621, DS92LX1622 SNLS327I – MAY 2010 – REVISED JANUARY 2014 www.ti.com Table 2. DS92LX1622 Control Registers (continued) Addr (Hex) Name Bits Field R/W Default 26 Remote Wake Enable 7:6 REM_WAKEUP_E N RW 0 11: Enable remote wake up mode 00: Normal operation mode Other values are NOT supported. 5:0 RESERVED RW 0 Reserved 7:0 BCC RW 0 0xE0: Normal Operation Mode. Users MUST program this value.
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DS92LX1621, DS92LX1622 www.ti.com SNLS327I – MAY 2010 – REVISED JANUARY 2014 FUNCTIONAL DESCRIPTION The DS92LX1621 / DS92LX1622 Channel Link III chipset is intended for camera applications. The Serializer/ Deserializer chipset operates from a 10 MHz to 50 MHz pixel clock frequency. The DS92LX1621 transforms a 16-bit wide parallel LVCMOS data bus along with a bi-directional control bus into a single high-speed differential pair.
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DS92LX1621, DS92LX1622 Bus Activity: Master SDA Line Register Address Slave Address 7-bit Address S Stop www.ti.com Start SNLS327I – MAY 2010 – REVISED JANUARY 2014 Data P 0 A C K A C K A C K Bus Activity: Slave S Register Address Slave Address 7-bit Address A C K Bus Activity: Slave Slave Address S 0 N A C K 7-bit Address A C K Stop SDA Line Start Bus Activity: Master Start Figure 25. Write Byte P 1 A C K Data Figure 26.
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DS92LX1621, DS92LX1622 www.ti.com SNLS327I – MAY 2010 – REVISED JANUARY 2014 CAD PIN ADDRESS DECODER The CAD pin is used to decode and set the physical slave address of the Serializer/Deserializer (I2C only) to allow up to six devices on the bus using only a single pin. The pin sets one of six possible addresses for each Serializer/Deserializer device. The pin must be pulled to VDD (1.
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DS92LX1621, DS92LX1622 SNLS327I – MAY 2010 – REVISED JANUARY 2014 www.ti.com To configure the devices for camera mode operation, set the Serializer M/S pin to LOW and the Deserializer M/S pin to HIGH. Before initiating any I2C commands, the Deserializer needs to be programmed with the target slave device addresses and Serializer device address. SER_DEV_ID Register 0x07h sets the Serializer device address and SLAVE_x_MATCH/SLAVE_x_INDEX registers 0x08h~0x17h set the remote target slave addresses.
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DS92LX1621, DS92LX1622 www.ti.com SNLS327I – MAY 2010 – REVISED JANUARY 2014 MULTIPLE DEVICE ADDRESSING Some applications require multiple camera devices with the same fixed address to be accessed on the same I2C bus. The DS92LX1621 / DS92LX1622 provide slave ID matching/aliasing to generate different target slave addresses when connecting more than two identical devices together on the same bus. This allows the slave devices to be independently addressed.
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DS92LX1621, DS92LX1622 SNLS327I – MAY 2010 – REVISED JANUARY 2014 www.ti.com I2C PASS THROUGH I2C pass-through provides an alternative means to independently address slave devices. The mode enables or disables I2C bidirectional control channel communication to the remote I2C bus. This option is used to determine whether or not an I2C instruction is to be transferred over to the remote I2C device.
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DS92LX1621, DS92LX1622 www.ti.com SNLS327I – MAY 2010 – REVISED JANUARY 2014 DS92LX1621 Camera A CMOS Image Sensor DS92LX1622 DATA PCLK DATA PCLK 2 I C Serializer A FSYNC FSO GPIO GPIO FSIN FSYNC 2 I C Deserializer A ECU Module Camera B CMOS Image Sensor DS92LX1621 DS92LX1622 DATA PCLK DATA PCLK 2 I C Serializer B FSYNC 2 FSO GPIO GPIO FSIN FSYNC PC I C Deserializer B Figure 32.
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DS92LX1621, DS92LX1622 SNLS327I – MAY 2010 – REVISED JANUARY 2014 www.ti.com AT-SPEED BIST (BISTEN, PASS) An optional AT SPEED Built in Self Test (BIST) feature supports at speed testing of the high-speed serial and the bidirectional control channel link. Control pins at the Deserializer are used to enable the BIST test mode and allow the system to initiate the test and set the duration. A HIGH on PASS pin indicates that all payloads received during the test were error free during the BIST duration test.
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DS92LX1621, DS92LX1622 www.ti.com SNLS327I – MAY 2010 – REVISED JANUARY 2014 The Deserializer GPIO[1:0] set to 00 will bypass the on-chip oscillator and an external oscillator to Serializer PCLK input is required. This allows the user to operate BIST under different frequencies other than the predefined ranges. Step 2: Enable AT SPEED BIST by placing the Serializer into BIST mode. The deserializer will communicate through the back-channel to configure Serializer into BIST mode.
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DS92LX1621, DS92LX1622 SNLS327I – MAY 2010 – REVISED JANUARY 2014 www.ti.com For instance, if BISTEN is held HIGH for 1 second and the PCLK is running at 43 MHz with 16 bpp, then the Bit Error Rate is no better than 1.46E-9. Step 4: Place system in Normal Operating Mode by disabling BIST at the Serializer. Once Step 3 is complete, AT SPEED BIST is over and the Deserializer is out of BIST mode. To fully return to Normal mode, apply Normal input data into the Serializer.
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DS92LX1621, DS92LX1622 www.ti.com SNLS327I – MAY 2010 – REVISED JANUARY 2014 SIGNAL QUALITY ENHANCERS Des - Receiver Input Equalization (EQ) The receiver inputs provided input equalization filter in order to compensate for loss from the media. The level of equalization is controlled via register setting. EMI REDUCTION Des - Receiver Staggered Output The Receiver staggered outputs allows for outputs to switch in a random distribution of transitions within a defined window.
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DS92LX1621, DS92LX1622 SNLS327I – MAY 2010 – REVISED JANUARY 2014 www.ti.com DS92LX1621 (SER) VDDIO VDDIO C12 FB1 C8 1.8V VDDT C4 FB2 C10 C5 FB3 C11 C6 FB4 C7 FB5 C3 DIN0 DIN1 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 DIN8 DIN9 DIN10 DIN11 DIN12 DIN13 HSYNC VSYNC LVCMOS Parallel Bus C9 C13 VDDPLL VDDCML VDDD C1 Serial Channel Link III Interface DOUT+ DOUTC2 PCLK 1.8V LVCMOS Control Interface MODE PDB 10 k: ID[X] GPIO Control Interface RID GPIO[0] GPIO[1] NOTE: C1 - C2 = 0.
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DS92LX1621, DS92LX1622 www.ti.com SNLS327I – MAY 2010 – REVISED JANUARY 2014 Figure 40 shows a typical connection of the DS92LX1622 Deserializer. DS92LX1622 (DES) 1.
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DS92LX1621, DS92LX1622 SNLS327I – MAY 2010 – REVISED JANUARY 2014 www.ti.com TRANSMISSION MEDIA The Ser/Des chipset is intended to be used over a wide variety of balanced cables depending on distance and signal quality requirements. The Ser/Des employ internal termination providing a clean signaling environment. The interconnect for Channel Link III interface should present a differential impedance of 100 Ohms.
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DS92LX1621, DS92LX1622 www.ti.com SNLS327I – MAY 2010 – REVISED JANUARY 2014 INTERCONNECT GUIDELINES For full details, see the Channel-Link PCB and Interconnect Design-In Guidelines (literature number SNLA008) and the Transmission Line RAPIDESIGNER Operation and Applications Guide (literature number SNLA035).
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DS92LX1621, DS92LX1622 SNLS327I – MAY 2010 – REVISED JANUARY 2014 www.ti.com REVISION HISTORY Changes from Revision H (April 2013) to Revision I Page • Changed "tri-state" and "low" OSS values to reflect correct bit definition .......................................................................... 20 • Added user-recommended value for deserializer echo cancellation in general-purpose cables ....................................... 24 • Added tolerance for transmission cable impedance ............
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 22-Nov-2013 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
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PACKAGE MATERIALS INFORMATION www.ti.com 22-Nov-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing DS92LX1621SQ/NOPB WQFN RTV 32 DS92LX1621SQE/NOPB WQFN RTV DS92LX1621SQX/NOPB WQFN RTV DS92LX1622SQ/NOPB WQFN DS92LX1622SQE/NOPB DS92LX1622SQX/NOPB SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1 32 250 178.0 12.4 5.3 5.3 1.3 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 22-Nov-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS92LX1621SQ/NOPB WQFN RTV 32 1000 213.0 191.0 55.0 DS92LX1621SQE/NOPB WQFN RTV 32 250 213.0 191.0 55.0 DS92LX1621SQX/NOPB WQFN RTV 32 4500 367.0 367.0 35.0 DS92LX1622SQ/NOPB WQFN RTA 40 1000 367.0 367.0 38.0 DS92LX1622SQE/NOPB WQFN RTA 40 250 213.0 191.0 55.
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MECHANICAL DATA RTA0040A SQA40A (Rev B) www.ti.
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MECHANICAL DATA RTV0032A SQA32A (Rev B) www.ti.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.