Datasheet

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DS99R105, DS99R106

www.ti.com

SNLS242D –MARCH 2007–REVISED APRIL 2013

DS99R105/DS99R106 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

Check for Samples: DS99R105, DS99R106

FEATURES

DESCRIPTION

The DS99R105/DS99R106 Chipset translates a 24-

• 3 MHz–40 MHz Clock Embedded and DC-

bit parallel bus into a fully transparent data/control

Balancing 24:1 and 1:24 Data Transmissions

LVDS serial stream with embedded clock information.

• Capable to Drive Shielded Twisted-Pair Cable

This single serial stream simplifies transferring a 24-

• User Selectable Clock Edge for Parallel Data

bit bus over PCB traces and cable by eliminating the

skew problems between parallel data and clock

on Both Transmitter and Receiver

paths. It saves system cost by narrowing data paths

• Internal DC Balancing Encode/Decode –

that in turn reduce PCB layers, cable width, and

Supports AC-Coupling Interface with no

connector size and pins.

External Coding Required

The DS99R105/DS99R106 incorporates LVDS

• Individual Power-Down Controls for Both

signaling on the high-speed I/O. LVDS provides a low

Transmitter and Receiver

power and low noise environment for reliably

• Embedded Clock CDR (Clock and Data

transferring data over a serial transmission path. By

Recovery) on Receiver and no External Source

optimizing the serializer output edge rate for the

of Reference Clock Needed

operating frequency range EMI is further reduced.

• All Codes RDL (Random Data Lock) to Support

In addition the device features pre-emphasis to boost

Live-Pluggable Applications

signals over longer distances using lossy cables.

Internal DC balanced encoding/decoding is used to

• LOCK Output Flag to Ensure Data Integrity at

support AC-Coupled interconnects.

Receiver Side

• Balanced T

SETUP

HOLD

between RCLK and

RDATA on Receiver Side

• PTO (Progressive Turn-On) LVCMOS Outputs

to Reduce EMI and Minimize SSO Effects

• All LVCMOS Inputs and Control Pins have

Internal Pulldown

• On-Chip Filters for PLLs on Transmitter and

Receiver

• Integrated 100Ω Input Termination on Receiver

• 4 mA Receiver Output Drive

• 48-Pin TQFP and 48-Pin WQFN Packages

• Pure CMOS .35 μm Process

• Power Supply Range 3.3V ± 10%

• Temperature Range 0°C to +70°C

• 8 kV HBM ESD Tolerance

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (29 pages)

PAGE 1
DS99R105, DS99R106 www.ti.com SNLS242D – MARCH 2007 – REVISED APRIL 2013 DS99R105/DS99R106 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer Check for Samples: DS99R105, DS99R106 FEATURES DESCRIPTION • The DS99R105/DS99R106 Chipset translates a 24bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information.
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DS99R105, DS99R106 SNLS242D – MARCH 2007 – REVISED APRIL 2013 www.ti.
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DS99R105, DS99R106 www.ti.com Absolute Maximum Ratings SNLS242D – MARCH 2007 – REVISED APRIL 2013 (1) (2) −0.3V to +4V Supply Voltage (VDD) LVCMOS/LVTTL Input Voltage −0.3V to (VDD +0.3V) LVCMOS/LVTTL Output Voltage −0.3V to (VDD +0.3V) LVDS Receiver Input Voltage −0.3V to 3.9V LVDS Driver Output Voltage −0.3V to 3.
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DS99R105, DS99R106 SNLS242D – MARCH 2007 – REVISED APRIL 2013 www.ti.com Electrical Characteristics (1) (2) (3) Over recommended operating supply and temperature ranges unless otherwise specified. Parameter Test Conditions Pin/Freq. Min Typ Max Units 2.0 1.5 VDD V GND 1.5 0.8 V −0.8 −1.5 V LVCMOS/LVTTL DC SPECIFICATIONS VIH High Level Voltage VIL Low Level Input Voltage VCL Input Clamp Voltage IIN Input Current ICL = −18 mA (4) VIN = 0V or 3.
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DS99R105, DS99R106 www.ti.com SNLS242D – MARCH 2007 – REVISED APRIL 2013 Electrical Characteristics(1)(2)(3) (continued) Over recommended operating supply and temperature ranges unless otherwise specified. Parameter Test Conditions Pin/Freq.
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DS99R105, DS99R106 SNLS242D – MARCH 2007 – REVISED APRIL 2013 www.ti.com Serializer Switching Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified.
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DS99R105, DS99R106 www.ti.com SNLS242D – MARCH 2007 – REVISED APRIL 2013 AC Timing Diagrams and Test Circuits Device Pin Name Signal Pattern TCLK ODD DIN EVEN DIN See Serializer Timing Requirements for TCLK Note (1). Figure 2. Serializer Input Checker-board Pattern Device Pin Name Signal Pattern RCLK ODD ROUT EVEN ROUT See Serializer Timing Requirements for TCLK Note (1). Figure 3.
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DS99R105, DS99R106 SNLS242D – MARCH 2007 – REVISED APRIL 2013 www.ti.com tTCP TCLK VDD/2 tDIS VDD/2 VDD/2 tDIH VDD DIN [0:23] Setup VDD/2 Hold VDD/2 0V See Serializer Timing Requirements for TCLK Note (2). Figure 6.
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DS99R105, DS99R106 www.ti.com SNLS242D – MARCH 2007 – REVISED APRIL 2013 2.0V PWDWN 0.8V tHZD or tLZD TCLK tZHD or tZLD tPLD DOUT± Output Active TRI-STATE TRI-STATE DIN SYMBOL N SYMBOL N+1 SYMBOL N+2 | | Figure 8.
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DS99R105, DS99R106 SNLS242D – MARCH 2007 – REVISED APRIL 2013 www.ti.com Single-ended Signal Deserializer 80% 80% 20% 8 pF lumped 20% tCLH tCHL Figure 12.
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DS99R105, DS99R106 www.ti.com SNLS242D – MARCH 2007 – REVISED APRIL 2013 2.0V PWDN 0.8V | | tDRDL RIN± LOCK }v[š TRI-STATE Œ TRI-STATE tHZR or tLZR ROUT [0:23] TRI-STATE TRI-STATE RCLK TRI-STATE TRI-STATE REN See Serializer Timing Requirements for TCLK Note (1). Figure 15.
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DS99R105, DS99R106 SNLS242D – MARCH 2007 – REVISED APRIL 2013 www.ti.com Ideal Data Bit End Sampling Window Ideal Data Bit Beginning RxIN_TOL -L RxIN_TOL -R Ideal Sampling Position tBIT ( ) 2 tBIT (1UI) RxIN_TOL_L is the ideal noise margin on the left of the figure, with respect to ideal. RxIN_TOL_R is the ideal noise margin on the right of the figure, with respect to ideal. TxOUT_E_O is affected by pre-emphasis value. Figure 17.
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DS99R105, DS99R106 www.ti.com SNLS242D – MARCH 2007 – REVISED APRIL 2013 DS99R105 Serializer Pin Descriptions Pin No. Pin Name I/O Description LVCMOS PARALLEL INTERFACE PINS 4-1, DIN[23:0] 48-44, 41-32, 29-25 LVCMOS_I Transmitter Parallel Interface Data Inputs Pins. Tie LOW if unused, do not float. 10 LVCMOS_I Transmitter Parallel Interface Clock Input Pin. Strobe edge set by TRFB configuration pin.
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DS99R105, DS99R106 SNLS242D – MARCH 2007 – REVISED APRIL 2013 www.ti.
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DS99R105, DS99R106 www.ti.com SNLS242D – MARCH 2007 – REVISED APRIL 2013 DS99R106 Deserializer Pin Descriptions (continued) Pin No. Pin Name I/O Description 17 LOCK LVCMOS_O LOCK indicates the status of the receiver PLL LOCK = H; receiver PLL is locked LOCK = L; receiver PLL is unlocked, ROUT[23-0] and RCLK are TRI-STATED 2 RESRVD LVCMOS_I RESERVED – This pin MUST be tied LOW.
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DS99R105, DS99R106 SNLS242D – MARCH 2007 – REVISED APRIL 2013 www.ti.com FUNCTIONAL DESCRIPTION The DS99R105 Serializer and DS99R106 Deserializer chipset is an easy-to-use transmitter and receiver pair that sends 24-bits of parallel LVCMOS data over a single serial LVDS link from 72 Mbps to 960 Mbps throughput. The DS99R105 transforms a 24-bit wide parallel LVCMOS data into a single high speed LVDS serial data stream with embedded clock.
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DS99R105, DS99R106 www.ti.com SNLS242D – MARCH 2007 – REVISED APRIL 2013 Serialized data and clock/control bits (24+4 bits) are transmitted from the serial data output (DOUT±) at 28 times the TCLK frequency. For example, if TCLK is , the serial rate is 40 x 28 = 1.12 Giga bits per second. Since only 24 bits are from input data, the serial “payload” rate is 24 times the TCLK frequency. For instance, if TCLK = 40 MHz, the payload data rate is 40 x 24 = 960 Mbps.
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DS99R105, DS99R106 SNLS242D – MARCH 2007 – REVISED APRIL 2013 www.ti.com AC-COUPLING AND TERMINATION The DS99R105 and DS99R106 supports AC-coupled interconnects through integrated DC balanced encoding/decoding scheme. To use AC coupled connection between the Serializer and Deserializer, insert external AC coupling capacitors in series in the LVDS signal path as illustrated in Figure 20.
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DS99R105, DS99R106 www.ti.com SNLS242D – MARCH 2007 – REVISED APRIL 2013 LIVE LINK INSERTION The Serializer and Deserializer devices support live pluggable applications. The “Hot Inserted” operation on the serial interface does not disrupt communication data on the active data lines. The automatic receiver lock to random data “plug & go” live insertion capability allows the DS99R106 to attain lock to the active data stream during a live insertion event.
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DS99R105, DS99R106 SNLS242D – MARCH 2007 – REVISED APRIL 2013 • • www.ti.com Minimize skew within the pair Terminate as close to the TX outputs and RX inputs as possible Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the TI web site at: http://www.ti.com/ww/en/analog/interface/lvds.shtml DOUT+ 100 nF 100 nF RIN+ 100: 100: DOUT- 100 nF RIN- 100 nF Figure 20.
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DS99R105, DS99R106 www.ti.com SNLS242D – MARCH 2007 – REVISED APRIL 2013 DS99R106 (DES) 3.3V 3.3V VDDPR0 VDDPR1 VDDIR C5 C1 VDDOR1 VDDOR2 VDDOR3 C6 RIN+ 100: RIN- ROUT8 ROUT9 ROUT10 ROUT11 ROUT12 ROUT13 ROUT14 ROUT15 C10 3.
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DS99R105, DS99R106 SNLS242D – MARCH 2007 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision C (April 2013) to Revision D • 22 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 16-Apr-2013 (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing DS99R105SQ/NOPB WQFN DS99R105SQX/NOPB DS99R105VSX/NOPB SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant NJU 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 WQFN NJU 48 2500 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 TQFP PFB 48 1000 330.0 16.4 9.3 9.3 2.2 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS99R105SQ/NOPB WQFN NJU DS99R105SQX/NOPB WQFN NJU 48 250 213.0 191.0 55.0 48 2500 367.0 367.0 38.0 DS99R105VSX/NOPB TQFP DS99R106SQ/NOPB WQFN PFB 48 1000 367.0 367.0 38.0 NJU 48 250 213.0 191.0 DS99R106SQX/NOPB 55.0 WQFN NJU 48 2500 367.0 367.0 38.0 DS99R106VSX/NOPB TQFP PFB 48 1000 367.
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MECHANICAL DATA NJU0048D SQA48D (Rev A) www.ti.
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MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°– 7° 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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