("" "!1 "!-('%& "!# )0$& &%"(#) %& SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 FEATURES D Supports Both DSD and PCM Formats D 24-Bit Resolution D Analog Performance: − Dynamic Range: 123 dB − THD+N: 0.0005% Differential Current Output: 4 mA p-p D D 8× Oversampling Digital Filter: − Stop-Band Attenuation: –98 dB − Pass-Band Ripple: ±0.
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 ORDERING INFORMATION PRODUCT PACKAGE PACKAGE CODE OPERATION TEMPERATURE RANGE PACKAGE MARKING DSD1796DB 28-lead SSOP 28DB –25°C to 85°C DSD1796 ORDERING NUMBER TRANSPORT MEDIA DSD1796DB Tube DSD1796DBR Tape and reel ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) DSD1796 VCC1, VCC2L, VCC2R VDD Supply voltage –0.3 V to 6.5 V –0.3 V to 4 V ±0.
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 ELECTRICAL CHARACTERISTICS (Continued) all specifications at TA = 25°C, VCC1 = VCC2L = VCC2R = 5 V, VDD = 3.3 V, fS = 44.
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 ELECTRICAL CHARACTERISTICS (Continued) all specifications at TA = 25°C, VCC1 = VCC2L = VCC2R = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data unless otherwise noted DSD1796DB PARAMETER TEST CONDITIONS MIN TYP UNIT MAX DSD MODE DYNAMIC PERFORMANCE (1) (2) (44.1 kHz, 64 fS) THD+N at FS 2 V rms Dynamic range –60 dB, EIAJ, A-weighted 0.
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 ELECTRICAL CHARACTERISTICS (Continued) all specifications at TA = 25°C, VCC1 = VCC2L = VCC2R = 5 V,, VDD = 3.3 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data unless otherwise noted DSD1796DB PARAMETER TEST CONDITIONS MIN TYP UNIT MAX POWER SUPPLY REQUIREMENTS VDD VCC1 VCC2L VCC2R Voltage range 3 3.3 3.6 VDC 4.75 5 5.25 VDC 7 9 fS = 44.
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www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 TYPICAL PERFORMANCE CURVES DIGITAL FILTER Digital Filter Response AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 0 5 0.0005 4 0.0004 −20 3 0.0003 −40 Amplitude – dB Amplitude – dB 2 0.0002 −60 −80 −100 1 0.0001 0 −1 –0.0001 −2 –0.0002 −120 −3 –0.0003 −140 −4 –0.0004 −160 0 1 2 3 4 −5 –0.0005 0.0 0.1 Frequency [× fS] 0.2 0.3 0.4 0.5 Frequency [× fS] Figure 1. Frequency Response, Sharp Rolloff Figure 2.
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 De-Emphasis Filter DE-EMPHASIS LEVEL vs FREQUENCY DE-EMPHASIS ERROR vs FREQUENCY 0 0.5 fS = 32 kHz −1 0.3 De-Emphasis Error – dB −2 De-Emphasis Level – dB fS = 32 kHz 0.4 −3 −4 −5 −6 −7 0.2 0.1 −0.0 0.0 −0.1 −0.2 −8 −0.3 −9 −0.4 −10 −0.5 0 2 4 6 8 10 12 14 0 2 4 6 f – Frequency – kHz Figure 5 10 12 14 Figure 6 DE-EMPHASIS LEVEL vs FREQUENCY DE-EMPHASIS ERROR vs FREQUENCY 0 0.5 fS = 44.
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 De-Emphasis Filter (Continued) DE-EMPHASIS LEVEL vs FREQUENCY DE-EMPHASIS ERROR vs FREQUENCY 0 0.5 fS = 48 kHz −1 0.3 De-Emphasis Error – dB De-Emphasis Level – dB −2 −3 −4 −5 −6 −7 0.2 0.1 −0.0 0.0 −0.1 −0.2 −8 −0.3 −9 −0.4 −10 −0.5 0 2 4 6 8 10 12 14 f – Frequency – kHz Figure 9 10 fS = 48 kHz 0.
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 ANALOG DYNAMIC PERFORMANCE Supply Voltage Characteristics TOTAL HARMONIC DISTORTION + NOISE vs SUPPLY VOLTAGE DYNAMIC RANGE vs SUPPLY VOLTAGE 126 124 Dynamic Range – dB THD+N – Total Harmonic Distortion + Noise – % 0.01 0.001 fS = 192 kHz fS = 48 kHz 4.75 5.00 5.25 fS = 192 kHz 120 116 4.50 5.50 VCC – Supply Voltage – V 5.00 5.25 5.
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 Temperature Characteristics TOTAL HARMONIC DISTORTION + NOISE vs FREE-AIR TEMPERATURE DYNAMIC RANGE vs FREE-AIR TEMPERATURE 126 124 Dynamic Range – dB THD+N – Total Harmonic Distortion + Noise – % 0.01 fS = 96 kHz 0.001 fS = 192 kHz fS = 48 kHz fS = 96 kHz fS = 48 kHz 122 fS = 192 kHz 120 118 0.
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 AMPLITUDE vs FREQUENCY 0 0 −20 −20 −40 −40 Amplitude – dB Amplitude – dB AMPLITUDE vs FREQUENCY −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 2 4 6 8 10 12 14 16 18 20 0 10 20 f – Frequency – kHz 30 NOTE: PCM mode, fS = 48 kHz, 32768 point 8 average, TA = 25°C, VDD = 3.3 V, VCC = 5 V, measurement circuit is Figure 32. Figure 19.
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 SYSTEM CLOCK AND RESET FUNCTIONS System Clock Input The DSD1796 requires a system clock for operating the digital interpolation filters and advanced segment DAC modulators. The system clock is applied at the SCK input (pin 7). The DSD1796 has a system clock detection circuit that automatically senses the frequency at which the system clock is operating. Table 1 shows examples of system clock frequencies for common audio sampling rates.
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 Power-On and External Reset Functions The DSD1796 includes a power-on reset function. Figure 24 shows the operation of this function. With VDD > 2 V, the power-on reset function is enabled. The initialization sequence requires 1024 system clocks from the time VDD > 2 V. After the initialization period, the DSD1796 is set to its default reset state, as described in the MODE CONTROL REGISTERS section of this data sheet.
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 AUDIO DATA INTERFACE Audio Serial Interface The audio interface port is a 3-wire serial port. It includes PLRCK (pin 4), PBCK (pin 6), and PDATA (pin 5). PBCK is the serial audio bit clock, and it is used to clock the serial data present on PDATA into the serial shift register of the audio interface. Serial data is clocked into the DSD1796 on the rising edge of PBCK. PLRCK is the serial audio left/right word clock.
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www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 External Digital Filter Interface and Timing The DSD1796 supports an external digital filter interface comprising a 3- or 4-wire synchronous serial port, which allows the use of an external digital filter. External filters include the Texas Instruments DF1704 and DF1706, the Pacific Microsonics PMD200, or a programmable digital signal processor.
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 SERIAL CONTROL INTERFACE The serial control interface is a 4-wire synchronous serial port, which operates asynchronously with the serial audio interface and the system clock (SCK). The serial control interface is used to program and read the on-chip mode registers. The control interface includes MDO (pin 13), MDI (pin 11), MC (pin 12), and MS (pin 10).
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 t(MHH) MS 1.4 V t(MSS) t(MCL) t(MCH) t(MSH) MC 1.4 V t(MCY) LSB MDI t(MDS) 1.
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 MODE CONTROL REGISTERS User-Programmable Mode Controls The DSD1796 includes a number of user-programmable functions which are accessed via mode control registers. The registers are programmed using the serial control interface, which is previously desribed in the SERIAL CONTROL INTERFACE section of this data sheet. Table 2 lists the available mode control functions, along with their default reset conditions and associated register index.
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 Register Map The mode control register map is shown in Table 3. Registers 16–21 include an R/W bit, which determines whether a register read (R/W = 1) or write (R/W = 0) operation is performed. Registers 22 and 23 are read-only. Table 3.
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 Register 18 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 R/W 0 0 1 0 0 1 0 ATLD FMT2 FMT1 FMT0 B3 B2 DMF1 DMF0 B1 B0 DME MUTE R/W: Read/Write Mode Select When R/W = 0, a write operation is performed. When R/W = 1, a read operation is performed. Default value: 0 ATLD: Attenuation Load Control This bit is available for read and write.
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 DME: Digital De-Emphasis Control This bit is available for read and write. Default value: 0 DME = 0 De-emphasis disabled (default) DME = 1 De-emphasis enabled The DME bit is used to enable or disable the de-emphasis function for both channels. MUTE: Soft Mute Control This bit is available for read and write.
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 OPE: DAC Operation Control This bit is available for read and write. Default value: 0 OPE = 0 DAC operation enabled (default) OPE = 1 DAC operation disabled The OPE bit is used to enable or disable the analog output for both channels. Disabling the analog outputs forces them to the bipolar zero level (BPZ) even if digital audio data is present on the input. ZOE: Zero Flag Pin Operation Control This bit is available for read and write.
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 Register 20 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 R/W 0 0 1 0 1 0 0 RSV SRST DSD DFTH MONO CHSL OS1 OS0 R/W: Read/Write Mode Select When R/W = 0, a write operation is performed. When R/W = 1, a read operation is performed. Default value: 0 SRST: System Reset Control This bit is available for write only.
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 OS[1:0]: Delta-Sigma Oversampling Rate Selection These bits are available for read and write. Default value: 00 OS[1:0] Operation Speed Select 00 64 times fS (default) 01 32 times fS 10 128 times fS 11 Reserved The OS bits are used to change the oversampling rate of delta-sigma modulation. Use of this function enables the designer to stabilize the conditions at the post low-pass filter for different sampling rates.
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 ZFGx: Zero-Detection Flag Where x = L or R, corresponding to the DAC output channel. These bits are available only for readback. Default value: 00 ZFGx = 0 Not zero ZFGx = 1 Zero detected When the DSD1796 detects that audio input data is continuously zero, the ZFGx bit is set to 1 for the corresponding channel(s).
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 APPLICATION INFORMATION TYPICAL CONNECTION DIAGRAM Cf 5V Rf 0.
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 C1 2700 pF R1 820 Ω VCC VCC C11 0.1 µF C17 22 pF 7 IOUT– 5 2 8 – 3 R5 200 Ω 6 + U1 NE5534 4 R3 220 Ω C3 8200 pF R7 180 Ω C5 27000 pF C15 0.1 µF C19 22 pF 7 2 3 5 – 6 + 4 C12 0.1 µF VEE R4 220 Ω R6 200 Ω 8 R8 180 Ω R9 100 Ω U3 NE5534 C16 0.1 µF C4 8200 pF VEE C2 2700 pF R2 820 Ω VCC C13 0.1 µF C18 22 pF 7 IOUT+ 2 3 5 – 8 6 + 4 U2 NE5534 VCC = 15 V VEE = –15 V fc = 50 kHz C14 0.1 µF VEE Figure 32.
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 C1 2200 pF R1 820 Ω VCC VCC C11 0.1 µF C17 22 pF 7 IOUT– 5 2 8 – 3 R5 150 Ω 6 + R3 91 Ω R10 120 Ω C3 22000 pF U1 NE5534 4 R8 75 Ω C5 8200 pF C4 27000 pF C15 0.1 µF C19 22 pF 7 2 3 5 – 6 + 4 C12 0.1 µF VEE R4 91 Ω R9 75 Ω R6 150 Ω 8 R11 120 Ω R7 100 Ω U3 NE5534 C16 0.1 µF C6 8200 pF VEE C2 2200 pF R2 820 Ω VCC C13 0.
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 IOUTL– (Pin 26) IOUT– Figure 32 Circuit IOUTL+ (Pin 25) OUT+ IOUT+ 3 1 2 IOUTR– (Pin 18) IOUT– Figure 32 Circuit IOUTR+ (Pin 17) IOUT+ OUT– Balanced Out Figure 34.
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 APPLICATION FOR EXTERNAL DIGITAL FILTER INTERFACE DFMS = 0 External Filter Device DSD1796 1 DSDL 2 DSDR 3 DBCK WDCK (Word Clock) 4 PLRCK DATA 5 PDATA BCK 6 PBCK SCK 7 SCK DFMS = 1 External Filter Device DSD1796 DATA_L 1 DSDL DATA_R 2 DSDR 3 DBCK 4 PLRCK 5 PDATA BCK 6 PBCK SCK 7 SCK WDCK (Word Clock) Figure 35.
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 Application for Interfacing With an External Digital Filter For some applications, it may be desirable to use an external digital filter to perform the interpolation function, as it can provide improved stop-band attenuation when compared to the internal digital filter of the DSD1796.
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 Audio Format The DSD1796 in the external digital filter interface mode supports right-justified audio formats including 16-bit, 20-bit, and 24-bit audio data, as shown in Figure 36. The audio format is selected by the FMT[2:0] bits of control register 18.
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 Functions Available in the External Digital Filter Mode The external digital filter mode is selected by setting DSD = 0 (register 20, B5) and DFTH = 1 (register 20. B4). The external digital filter mode allows access to the majority of the DSD1796 mode control functions.
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 APPLICATION FOR DSD FORMAT (DSD MODE) INTERFACE DSD Decoder DSD1796 DATA_L 1 DSDL DATA_R 2 DSDR Bit Clock 3 DBCK 4 PLRCK 5 PDATA 6 PBCK 7 SCK System Clock (1) (1) The system clock can be removed after setting the register to the DSD mode. Figure 38. Connection Diagram in DSD Mode Feature This mode is used for interfacing directly to a DSD decoder, which is found in Super Audio CDt (SACD) applications.
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 Requirements for Bit Clock and System Clock In the DSD mode, the bit clock (DBCK) is required on pin 3 of the DSD1796. The frequency of the bit clock can be N times the sampling frequency. Generally, N is 64 in DSD applications. The interface timing between the bit clock and DSDL and DSDR is required to meet the same setup-and hold-time specifications as shown in Figure 40.
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 ANALOG FIR FILTER PERFORMANCE IN DSD MODE GAIN vs FREQUENCY GAIN vs FREQUENCY 0 0 −1 −10 −2 −20 Gain – dB Gain – dB fc = 185 kHz Gain(1) = –6.6 dB −3 −30 −4 −40 −5 −50 −6 −60 0 50 100 150 200 0 500 f – Frequency – kHz 1000 1500 f – Frequency – kHz Figure 41. DSD Filter-1, Low BW Figure 42.
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 ANALOG FIR FILTER PERFORMANCE IN DSD MODE (CONTINUED) GAIN vs FREQUENCY GAIN vs FREQUENCY 0 0 −1 −10 −2 −20 Gain – dB Gain – dB fc = 85 kHz Gain(1) = –1.5 dB −3 −30 −4 −40 −5 −50 −60 −6 0 50 100 150 0 200 500 1000 1500 f – Frequency – kHz f – Frequency – kHz Figure 45. DSD Filter-3, Low BW Figure 46.
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 DSD MODE CONFIGURATION AND FUNCTION CONTROLS Configuration for the DSD Interface Mode The DSD interface mode is selected by setting DSD = 1 (register 20, B5).
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 TDMCA INTERFACE FORMAT The DSD1796 supports the time-division-multiplexed command and audio (TDMCA) data format to simplify the host control serial interface. The TDMCA format is designed not only for the McBSP of TI DSPs but also for any programmable devices. The TDMCA format can transfer not only audio data but also command data, so that it can be used together with any kind of device that supports the TDMCA format.
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 Device ID Determination The TDMCA mode also supports a multichip implementation in one system. This means a host controller (DSP) can simultaneously support several TDMCA devices, which can be of the same type or different types, including PCM devices. The PCM devices are categorized as IN device, OUT device, IN/OUT device, and NO device.
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 DCII LRCK BCK IN/OUT Device (DIX1700) DCOI DI DCIO DO DCOO Device ID = 1 LRCK BCK IN Device (DSD1796) DI DO LRCK DCI DCO Device ID = 2 NO Device DCI BCK DI DO DCO Device ID = 3 • • • FSX FSR CLKX CLKR DX DR LRCK OUT Device DCI BCK DI DO DCO Device ID = 2 TI DSP LRCK OUT Device DCI BCK DI DO DCO Device ID = 3 • • • Figure 51.
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 LRCK BCK DID DI Device ID = 1 DCO1 Device ID = 2 DCO1 DCI2 Command Field Device ID = 3 DCO2 DCI3 • • • • • • Device ID = 30 DCO29 DCI30 58 BCKs Figure 52. Device ID Determination Sequence TDMCA Frame In general, the TDMCA frame consists of the command field, extended command (EMD) field, and audio data fields. All of them are 32 bits in length, but the lowest byte has no meaning. The MSB is transferred first for each field.
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 1/fS (256 BCK Clocks) 7 Packets × 32 Bits LRCK BCK DI Ch1 CMD Ch2 Ch3 Ch4 Ch5 Ch6 Don’t Care CMD IN and OUT Channel Orders are Completely Independent DO Ch1 CMD Ch2 Figure 54. TDMCA Frame Example of 6-Ch DAC and 2-Ch ADC With Command Read Command Field The normal command field is defined as follows.
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 Audio Fields The audio field is 32 bits in length and the audio data is transferred MSB first, so the other fields must be stuffed with 0s as shown in the following example. 31 Audio Data 16 MSB 12 8 24 Bits 7 LSB 4 3 0 All 0s TDMCA Register Requirements TDMCA mode requires device ID and audio channel information, previously described.
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 1/fS (384 BCK Clocks) 9 Packets × 32 Bits LRCK BCK IN Daisy Chain CMD DI Ch1 Ch2 Ch3 Ch4 Ch5 Ch6 Ch7 Ch8 Don’t Care DCI1 DID = 1 DID = 2 DID = 3 DID = 4 DCO1 DCI2 DCO2 DCI3 DCO3 DCI4 DCO4 Figure 56.
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 Command Packet LRCK BCK DI DID EMD DCO1 DCO2 • • • Figure 58.
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 LRCK t(LB) t(BL) BCK t(BCY) t(DS) t(DH) DI t(DOE) DO t(DS) t(DH) DCI t(COE) DCO PARAMETER t(BCY) BCK pulse cycle time t(LB) LRCK setup time MIN MAX UNITS 20 ns 0 ns t(BL) t(DS) LRCK hold time 3 ns DI setup time 0 ns t(DH) t(DS) DI hold time 3 ns DCI setup time 0 ns 3 ns t(DH) DCI hold time t(DOE) DO output delay(1) t(COE) DCO output delay(1) (1) Load capacitance is 10 pF. Figure 59.
www.ti.com SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 ANALOG OUTPUT Table 5 and Figure 60 show the relationship between the digital input code and analog output. Table 5. Analog Output Current and Voltage 800000 (–FS) 000000 (BPZ) 7FFFFF (+FS) IOUTN [mA] IOUTP [mA] –1.5 –3.5 –5.5 –5.5 –3.5 –1.5 VOUTN [V] VOUTP [V] –1.23 –2.87 –4.51 –4.51 –2.87 –1.23 VOUT [V] –2.98 0 2.
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PACKAGE MATERIALS INFORMATION www.ti.com 13-Jun-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device DSD1796DBR Package Package Pins Type Drawing SSOP DB 28 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2000 330.0 17.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 8.5 10.8 2.4 12.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 13-Jun-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DSD1796DBR SSOP DB 28 2000 336.6 336.6 28.
MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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PACKAGE MATERIALS INFORMATION www.ti.com 13-Jan-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device DSD1796DBR Package Package Pins Type Drawing SSOP DB 28 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 17.4 Pack Materials-Page 1 8.5 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.8 2.4 12.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 13-Jan-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DSD1796DBR SSOP DB 28 2000 336.6 336.6 28.
MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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