TMS320F20x/F24x DSP Embedded Flash Memory Technical Reference This document contains preliminary data current as of publication date and is subject to change without notice.
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PRELIMINARY Preface Read This First About This Manual This reference guide describes the operation of the embedded flash EEPROM module on the TMS320F20x/F24x digital signal processor (DSP) devices and provides sample code that you can use in developing your own software. The performance specifications of the embedded flash memory have been evaluated using the algorithms and techniques described in this guide.
PRELIMINARY If you are looking for information about: Turn to these locations: Over-erasure (depletion) and recovery Section 1.1, Basic Concepts of Flash Memory Technology Section 2.7, Recovering From Over-Erasure (Flash-Write Operation) Section 3.4, Flash-Write Algorithm Programming the flash array Section 1.1, Basic Concepts of Flash Memory Technology Section 2.1, Modifying the Contents of the TMS320F20x/F24x Flash Array Section 2.5, Program Operation Section 3.
PRELIMINARY Related Documentation From Texas Instruments Related Documentation From Texas Instruments The following books describe the ’F20x/24x and related support tools. To obtain a copy of any of these TI documents, call the Texas Instruments Literature Response Center at (800) 477–8924. When ordering, please identify the book by its title and literature number.
Related Documentation From Texas Instruments PRELIMINARY TMS320C2xx C Source Debugger User’s Guide (literature number SPRU151) tells you how to invoke the ’C2xx emulator and simulator versions of the C source debugger interface. This book discusses various aspects of the debugger interface, including window management, command entry, code execution, data management, and breakpoints. It also includes a tutorial that introduces basic debugger functionality.
PRELIMINARY If You Need Assistance . . . If You Need Assistance . . . - World-Wide Web Sites TI Online Semiconductor Product Information Center (PIC) DSP Solutions 320 Hotline On-linet - http://www.ti.com http://www.ti.com/sc/docs/pic/home.htm http://www.ti.com/dsps http://www.ti.com/sc/docs/dsps/support.htm North America, South America, Central America Product Information Center (PIC) (972) 644-5580 TI Literature Response Center U.S.A.
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Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć1 Discusses basic flash memory technology; summarizes the features and benefits of the TMS320F20x/F24x flash module 1.1 1.2 1.3 2 Flash Operations and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents A.2 A.3 A.4 A.5 A.6 x A.1.1 Header File for Constants and Variables, SVAR20.H . . . . . . . . . . . . . . . . . . . . . AĆ2 A.1.2 Clear Algorithm, SCLR20.ASM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AĆ5 A.1.3 Erase Algorithm, SERA20.ASM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AĆ10 A.1.4 Flash-Write Algorithm, SFLW20.ASM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AĆ15 A.1.
Figures Figures 1–1 2–1 2–2 2–3 3–1 3–2 3–3 3–4 3–5 3–6 3–7 TMS320F20x/F24x Program Space Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć4 Flash Memory Logic Levels During Programming and Erasing . . . . . . . . . . . . . . . . . . . . . . 2Ć4 Memory Maps in Register and Array Access Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Ć6 Segment Control Register (SEG_CTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tables Tables 1–1 2–1 2–2 2–3 2–4 3–1 3–2 3–3 xii TMS320 Devices With On-Chip Flash EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć3 Operations that Modify the Contents of the Flash Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Ć4 Flash Module Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Ć8 Segment Control Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . .
PRELIMINARY Chapter 1 Introduction The TMS320F20x/F24x digital signal processors (DSPs) contain on-chip flash EEPROM (electrically-erasable programmable read-only memory). The embedded flash memory provides an attractive alternative to masked program ROM. Like ROM, flash memory is nonvolatile, but it has an advantage over ROM: in-system reprogrammability.
Basic Concepts of Flash Memory Technology PRELIMINARY 1.1 Basic Concepts of Flash Memory Technology The term flash in this EEPROM technology refers to the speed of some of the operations performed on the memory (these operations will be described in greater detail later in this document). An entire block of bits is affected simultaneously in a block or flash operation, rather than being affected one bit at a time.
PRELIMINARY TMS320F20x/F24x Flash Module 1.2 TMS320F20x/F24x Flash Module The ’F20x/F24x flash EEPROM is implemented with one or two independent flash memory modules of 8K or 16K words. Each flash module is composed of a flash memory array, four control registers, and circuitry that produces analog voltages for programming and erasing. The flash array size of the TMS320F206 and TMS320F240 is 16K × 16 bits, while the TMS320F241 and TMS320F243 incorporate an 8K × 16-bit flash array (see Table 1–1).
PRELIMINARY TMS320F20x/F24x Flash Module Simplified memory maps for the program space of the TMS320F20x/F24x devices are shown in Figure 1–1 to illustrate the location of the flash modules. Figure 1–1.
PRELIMINARY Benefits of Embedded Flash Memory in a DSP System 1.3 Benefits of Embedded Flash Memory in a DSP System The circuitry density of flash memory is about half that of conventional EEPROM memory, making it possible to approach DRAM densities with flash memory. This increased density allows flash memory to be integrated with a CPU and other peripherals in a single ’F20x/F24x DSP chip.
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PRELIMINARY Chapter 2 Flash Operations and Control Registers The operations that modify the contents of the ’F20x/F24x flash array are performed in software through the use of dedicated programming algorithms. This chapter introduces the operations performed by these algorithms and explains the role of the control registers in this process. The actual algorithms are discussed in Chapter 3. Topic PRELIMINARY Page 2.1 Operations that Modify the Contents of the ’F20x/F24x Flash Array . . . . . . . . . .
Operations that Modify the Contents of the ’F20x/F24x Flash Array PRELIMINARY 2.1 Operations that Modify the Contents of the ’F20x/F24x Flash Array Operations that modify the contents of the flash array are generically referred to as either “programming,” which drives one or more bits toward the logic zero state, or “erasing,” which drives all bits towards the logic one state.
PRELIMINARY Operations that Modify the Contents of the ’F20x/F24x Flash Array This procedure is discussed in complete detail in Chapter 3. During these operations that are used to modify the contents of the flash array, three special read modes, and a corresponding set of reference voltage levels, are used when reading back data values to verify programming and erase operations.
PRELIMINARY Operations that Modify the Contents of the ’F20x/F24x Flash Array Figure 2–1. Flash Memory Logic Levels During Programming and Erasing Depletion Mode Inverse Erase Reference Level Logic 1 Program operations VER1 Reference Level Clear Program 1 Margin Flash Write (Towards logic zero level) Erase (Towards logic one level) Erase operation 0 Margin VER0 Reference level Logic 0 Table 2–1.
PRELIMINARY Accessing the Flash Module 2.2 Accessing the Flash Module In addition to the flash memory array, each flash module has four registers that control operations on the flash array.
PRELIMINARY Accessing the Flash Module Figure 2–2. Memory Maps in Register and Array Access Modes Flash access control register (single bit) MODE = 1: Array-access mode MODE = 0: Register access mode 0100 ... 010 0100 ... 011 SEG_CTR register TST register WADRS register WDATA register 4 registers duplicated Flash memory array 4 registers duplicated 1110 ...110 0110 ...111 2.2.
PRELIMINARY Accessing the Flash Module Although the function is the same, the access control registers of the ’F206 device are mapped at different addresses from that of the ’F24x devices, and their values are modified in a different way. 2.2.2 TMS320F24x Flash Access-Control Register The access-control register of the ’F24x devices is a special type of I/Omapped register that cannot be read. The register is mapped at I/O address 0FF0Fh, and it functions as indicated below.
PRELIMINARY Flash Module Control Registers 2.3 Flash Module Control Registers Table 2–2 lists the control registers and their relative addresses within the four locations that repeat throughout the module’s address range. Table 2–2. Flash Module Control Registers Described in ... Relative Address Register Name Description Section Page 0 SEG_CTR Segment control register. The eight MSBs enable specific segments for programming. Setting a bit to 1 enables the segment.
PRELIMINARY Flash Module Control Registers Table 2–3. Segment Control Register Field Descriptions Bits Name Description 15–8 SEG7–SEG0 Segment enable bits. Each of these bits protects the specified segment against programming or enables programming for the specified segment in the array. Any number of segments (from 0 to 7 in any combination) can be enabled at any one time. See Table 2–4 for segment address ranges. EXE must be cleared to modify the SEGx bits.
PRELIMINARY Flash Module Control Registers Table 2–4.
PRELIMINARY 2.3.4 Flash Module Control Registers Write Data Register (WDATA) The write data register (WDATA) is a 16-bit register that contains the latched write data for a programming operation. In array-access mode, this register can be loaded by writing a data value to the flash module. It can be loaded directly in register-access mode by writing to it. The WDATA register must be loaded with the value FFFFh before an erase operation starts.
PRELIMINARY Read Modes 2.4 Read Modes The ’F20x/F24x flash module uses four read modes and corresponding sets of reference levels: Standard Verify 0s (VER0) Verify 1s (VER1) Inverse-erase Read mode selection is accomplished through the verify bits (bits 3 and 4) in SEG_CTR during execution of the algorithms. In the standard read mode of the ’F20x/F24x flash module, the supply voltage (VDD) is internally applied to the cell to select it for reading.
PRELIMINARY Program Operation 2.5 Program Operation The program operation of the ’F20x/F24x flash module loads the applicationspecific data (a pattern of 0s) into the flash array. The basis of the operation is applying a program pulse to a single word of flash memory. The term program pulse refers to the time during the program operation between the setting and the clearing of the EXE bit ( bit 0 of SEG_CTR). During the program pulse, charge is added to the addressed bits via the programming mechanism.
PRELIMINARY Erase Operation 2.6 Erase Operation The erase operation of the ’F20x/F24x flash module prepares the flash array for programming and enables reprogrammability of the flash array. Before the array can be erased, all bits must be programmed to 0s. This procedure of programming all array locations in preparation for the erase is called clearing the array. During the erase, all bits in the array are changed from 0s to 1s.
PRELIMINARY Recovering From Over-Erasure (Flash-Write Operation) 2.7 Recovering From Over-Erasure (Flash-Write Operation) Generally, not all bits in the flash array have the same amount of charge removed with each erase pulse. By the time all bits have reached the VER1 read margin (and erase is complete), some of the bits in the array may be overerased. They are said to be in depletion mode.
PRELIMINARY Reading From the Flash Array 2.8 Reading From the Flash Array Once the array is programmed, it is read in the same manner as other memory devices on the DSP memory interface. The flash module operates with zero wait states. When you are reading the flash module, the flash segment control register (SEG_CTR) bits should be 0 and the flash array must be in the arrayaccess mode. 2.
PRELIMINARY Chapter 3 Algorithm Implementations and Software Considerations This chapter discusses the implementations of the algorithms for performing the operations described in the previous chapter. It also discusses items you must consider when incorporating the algorithms into your ’F20x/F24x DSP application code. Topic PRELIMINARY Page 3.1 How the Algorithms Fit Into the Program-Erase-Reprogram Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
How the Algorithms Fit Into the Program-Erase-Reprogram Flow PRELIMINARY 3.1 How the Algorithms Fit Into the Program-Erase-Reprogram Flow The algorithms discussed in this chapter can be used to reprogram the ’F20x/F24x flash module multiple times. The clear algorithm, erase algorithm, and flash-write algorithm are used to prepare the flash memory for programming, while the programming algorithm is used to write a desired pattern of 0s to the array (program the array).
PRELIMINARY How the Algorithms Fit Into the Program-Erase-Reprogram Flow Figure 3–1.
PRELIMINARY Programming (or Clear) Algorithm 3.2 Programming (or Clear) Algorithm The programming algorithm sequentially writes any number of addresses with a specified bit pattern.This algorithm is used to program application code or data into the flash array. With a slight modification, the same algorithm performs the clear portion of the initialization flow (i.e., programs all bits to zero). In this role, the algorithm is called the clear algorithm.
PRELIMINARY Programming (or Clear) Algorithm The main feature of the program/clear algorithm is the concept of programming an entire row of bits in a group. The ’F20x/F24x flash array is organized in rows of 32 words. That is, addresses 0000h through 001Fh are physically located on the same row of the flash memory array. The array is designed so that there is a dependence between the charge levels on adjacent (even–odd) addresses during programming.
PRELIMINARY Programming (or Clear) Algorithm Figure 3–3.
PRELIMINARY Programming (or Clear) Algorithm Another important consideration is the total amount of time required to do the programming. The number of programming pulses required to completely program a flash memory cell increases as ambient temperature increases and/or supply voltage decreases. More programming pulses are required when the minimum supply voltage is used than when the nominal or maximum supply voltage is used.
PRELIMINARY Programming (or Clear) Algorithm Table 3–1. Steps for Verifying Programmed Bits and Applying One Program or Clear Pulse (Continued) Step Action Description 7 Mask the data to program Mask any bits in the lower byte that do not require programming (are allower byte. ready read as zero), and mask off upper byte. Recall that the algorithm should mask one byte while programming the other because a maximum of eight bits can be programmed simultaneously.
PRELIMINARY Programming (or Clear) Algorithm Before each program pulse is applied, a read of the byte is performed to determine which bits have reached the programmed level. Any bits that have reached the programmed level are masked (set to 1 in the WDATA register). This method of programming provides uniform charge levels among programmed bits, whereas using a single, long program pulse could result in some bits having much more charge than others.
PRELIMINARY Erase Algorithm 3.3 Erase Algorithm The erase algorithm follows the clear algorithm in executing the entire initialization flow. Figure 3–4 highlights the erase algorithm’s place in the overall flow. Figure 3–4.
PRELIMINARY Erase Algorithm Table 3–2. Steps for Applying One Erase Pulse Step Action Description 1 Power up the VCCP pin. Set VCCP pin to VDD. If the VCCP pin for the flash module to be erased is not set to VDD, then the array will not be erased properly. 2 Load WDATA register with This load overrides the erase protection mechanism. FFFFh. 3 Activate the erase mode and Set the WRITE/ERASE field to 01 and set SEG0–SEG7 bits in the enable segments. SEG_CTR register.
PRELIMINARY Erase Algorithm 4) The actual address is restored. 5) The contents of the restored address are read. The advantage of this approach is that it forces the worst-case switching condition on the flash addressing logic during the reads, thus improving the margin of the erase. Address complementing on the ’F20x/F24x can be accomplished easily by using the XOR instruction to complement the bits of the address.
PRELIMINARY Erase Algorithm Figure 3–5. Erase Algorithm Flow Start (all words=0000h) Set VER1 bit in SEG_CTR Wait for td(BUSY-VERIFY) Verify erase Read all locations using address complementing Clear all bits in SEG_CTR Á Á All words = FFFFh ? Yes Set VER0 and VER1 bits in SEG_CTR No Apply one erase pulse to flash array (see Table 3–2) Wait for td(BUSY-INVERSE) Read first 32 words No Erase pulse count ≥ Max† ? No Yes † See the device data sheet for the timing parameter values.
PRELIMINARY Flash-Write Algorithm 3.4 Flash-Write Algorithm The flash-write operation recovers bits in depletion mode, which can be caused by over-erasure. The flash-write algorithm’s place in the overall flow is highlighted in Figure 3–6. Figure 3–6.
PRELIMINARY Flash-Write Algorithm Table 3–3. Steps for Applying One Flash-Write Pulse Steps Action Description 1 Power up the VCCP pin. Set the VCCP pin to VDD. If the VCCP pin for the flash module to be recovered is not set to VDD, then the flash-write operation will not be effective. 2 Activate the flash-write Set the WRITE/ERASE field to 10 and set SEG0–SEG7 in the mode and enable all seg- SEG_CTR register. The flash module must be in register access ments. mode (see section 2.2).
PRELIMINARY Flash-Write Algorithm Figure 3–7. Flash-Write Algorithm Flow Start Set VER0 and VER1 bits in SEG_CTR Wait for td(RD-VERIFY) Depletion check Read first 32 words All 32 words = 0000h? Yes No Apply one flash-write pulse to flash array (see Table 3–3) No Flash-write pulse count ≥ Max† ? Yes † See the device data sheet for the timing parameter values.
PRELIMINARY Flash-Write Algorithm The CPU frequency range for the application is an important consideration for the depletion test, as well as for the program and erase operations. Because of the actual implementation of the flash memory circuitry, a bit in depletion mode is most easily detected at low frequency. Accordingly, if the application requires a variable CPU clock rate, the depletion test should be performed at the lowest frequency in the range.
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PRELIMINARY Appendix AppendixAA Assembly Source Listings and Program Examples The flash array is erased and programmed by code running on the DSP core. This code can originate from off-chip memory or can be loaded into on-chip RAM. The available flash programming tools for the ’F20x/F24x allow you to program the on-chip flash module without having knowledge or visibility of the algorithms.
Assembly Source for Algorithms PRELIMINARY A.1 Assembly Source for Algorithms The algorithm source files implement the flows given in Chapter 3. Each algorithm is written as an assembly language subroutine, beginning with a label at an entry point and ending with a return instruction. The algorithms share a set of 16 relocatable variables for which pointers are defined in the header file, SVAR20.H.
PRELIMINARY Assembly Source for Algorithms ************************************************************** ** Variable declaration file ** * ** * TMS320F2XX Flash Utilities. ** * Revision: 2.0, 9/10/97 ** * Revision: 2.1, 1/31/98 ** * ** * Filename: svar20.asm ** * ** *Note: ** *DLOOP is a delay loop variable used in flash algorithms. ** *This is a function of CLKOUT1. If the F206 device runs at ** *any CLKOUT1 speed other than 20 MHz, DLOOP value should be ** *redefined per the equation explained below.
Assembly Source for Algorithms PRELIMINARY *CONSTANTS * ********************************************************* *Conditional assembly variable for F24X vs F206. * *If F24X = 1, then assemble for F24X; otherwise, * *assemble for F206. * ********************************************************* F24X .set 0 ;Assemble for F206 ;F24X .set 1 ;Assemble for F24X *********************************************** * Delay variables for CLEAR,ERASE and PROGRAM * *********************************************** D5 .
PRELIMINARY Assembly Source for Algorithms A.1.2 Clear Algorithm, SCLR20.ASM This code is an implementation of the clear (programming) algorithm described in section 3.2 on page 3-4. Recall that the clear algorithm is identical to the programming algorithm with the data forced to 0000h for all flash addresses. Memory section: fl_clr Entry point: GCLR Parameters to be declared and initialized by the calling code are: PROTECT defines the values of bits 8–15 of SEG_CTR during the clear algorithm.
Assembly Source for Algorithms PRELIMINARY * programmed bits. For example, if the flash is programmed * * using a CLKOUT period of 50 ns, the flash can be read back * reliably over the CLKOUT period range of 50 ns to 150 ns * * (6.67 MHz–20 MHz). The programming pulse-duration is * * 100 us, and a maximum of 150 pulses is applied per row. * * * * The following resources are used for temporary storage: * * AR0 Used for comparisons * * AR1 Used for pgm pulse count * * AR2 Used for row banz loop.
PRELIMINARY Assembly Source for Algorithms SACL LACL FL_ST ;Save array start address. FL_ADRS ;Get segment start address. NEWROW ;********Begin a new row.* SACL BASE_1 ;Save row start address. LAR AR1,#0 ;Init pulse count to zero. SAMEROW ;********Same row, next pulse.* SPLK #1,BASE_0 ;Set row done flag = 1(True). LACL BASE_1 ;Get row start address. SACL FL_ADRS ;Save as current address. LAR AR2,#31 ;Init row index. ********Repeat the following code 32 times until end of row.
Assembly Source for Algorithms PRELIMINARY * SPAD2 Flash program + EXE command.
PRELIMINARY Assembly Source for Algorithms TBLW SPAD1 ;EXECUTE COMMAND * LAR AR6,#D10 ;SET DELAY * CALL DELAY,*,AR6 ;WAIT * CALL ARRAY ;ACCESS FLASH ARRAY * RET ;RETURN TO CALLING SEQUENCE* ************************************************************* ************************************************* * PRG_BYTE: Programs hi or lo byte depending on * * byte mask (BASE_2). * ************************************************* PRG_BYTE: CALL SET_RD_VER0 ;Read word at VER0 level.
Assembly Source for Algorithms PRELIMINARY A.1.3 Erase Algorithm, SERA20.ASM This code is an implementation of the erase algorithm described in section 3.3 on page 3-10. Memory section: fl_ers Entry point: GERS Parameters to be declared and initialized by the calling code are: PROTECT defines the values of bits 8–15 of SEG_CTR during the erase algorithm. SEG_ST defines the start address of the flash array to be erased. SEG_END defines the end address of the flash array to be erased.
PRELIMINARY Assembly Source for Algorithms * The erase pulse duration is 7ms, and a maximum of ** * 1000 pulses is applied to the array. ** * ** * The following resources are used for temporary storage: ** * AR0 Used for comparisons ** * AR1 Used for erase pulse count ** * AR2 Used for main banz loop ** * AR6 Parameter passed to DELAY ** * BASE_0 Parameter passed to Set_mode ** * BASE_1 Used for flash address.
Assembly Source for Algorithms PRELIMINARY CLRC OVM ;Disable overflow mode. LACL SEG_ST ;Get segment start address. AND #04000h ;Get array start address. SACL FL_ST ;Save array start address. OR #03FFFh ;Get array end address. SACL FL_END ;Save array end address. SPLK #0,ERROR ;Reset error flag LAR AR1,#0 ;Set erase count to 0. SPLK #STOP, BASE_0 ;Stop command. CALL SET_MODE ;Disable any flash cmds. XOR_ERASE ** Compute checksum for flash, using address complementing.
PRELIMINARY Assembly Source for Algorithms ***** If here, then an error has occurred. EXIT SPLK #1,ERROR ;Update error flag SPLK #STOP,BASE_0 ;Stop command. CALL SET_MODE ;Disable any flash cmds. B DONE ;Get outa here. ************************************************************ .page ************************************************** * SET_MODE: This routine sets the flash in the * * mode specified by the contents of BASE_0. This * * can be used for VER0,VER1,INVERASE, or STOP.
Assembly Source for Algorithms PRELIMINARY * * * The following resources are used for temporary storage: * * BASE_0 Flash STOP command, and FFFF for WDATA. * * BASE_5 Flash erase command. * * BASE_6 Flash erase + EXE command. * ************************************************************* ERASE_A * SET UP FLASH ERASE COMMANDS FOR PROTECT MASK.
PRELIMINARY Assembly Source for Algorithms A.1.4 Flash-Write Algorithm, SFLW20.ASM This code is an implementation of the flash-write algorithm described in section 3.4 on page 3-14. Memory section: fl_wrt Entry point: FLWS Parameters to be declared and initialized by the calling code are: PROTECT defines the values of bits 8–15 of SEG_CTR during the flashwrite algorithm. SEG_ST defines the start address of the flash array to be recovered. SEG_END defines the end address of the flash array to be recovered.
Assembly Source for Algorithms PRELIMINARY * BASE_3 Used for EXE + flw cmd * ************************************************************** .include ”svar20.h” ;defines variables for flash0 ;or for flash1 array * MAX_FLW .set 10000 ;Allow only 10000 flw pulses. INV_ER .set 018h ;INVERSE ERASE COMMAND WORD FLWR .set 6 ;FLASH WRITE COMMAND WORD FLWR_EX .set 047h ;FLASH WRITE EXEBIN COMMAND WORD STOP .set 0 ;RESET REGISTER COMMAND WORD .def FLWS .ref PROTECT,SEG_ST,SEG_END .ref DELAY,REGS,ARRAY .
PRELIMINARY Assembly Source for Algorithms BCND FL_WRITE, NEQ ;If ACC<>0, then flwrite. *Else, continue until until done with row. BANZ NEXT_IVERS ;Loop 32 times. SPLK #STOP,BASE_0 ;Flash STOP command. CALL SET_MODE ;Disable flash commands. ;If here then test passed. DONE RET ;Return to calling code. * If here, then an error has occurred. EXIT SPLK #1,ERROR ;Update error flag SPLK #STOP,BASE_0 ;Flash STOP command. CALL SET_MODE ;Disable flash commands. CALL ARRAY ;ACCESS FLASH ARRAY B DONE ;Get outa here.
Assembly Source for Algorithms PRELIMINARY LAR AR0,#MAX_FLW CMPR 2 ;If AR1>MAX_FLW then BCND EXIT,TC ;Fail, don’t continue recovery. B INV_ERASE ;Else, perform iverase again. ************************************************** * SET_MODE: This routine sets the flash in the * * mode specified by the contents of BASE_0. This * * can be used for VER0,VER1,INVERASE,or STOP. * ************************************************** SET_MODE CALL REGS ;ACCESS FLASH REGS LACL FL_ST ;ACC => SEG_CTR.
PRELIMINARY Assembly Source for Algorithms A.1.5 Programming Algorithm, SPGM20.ASM This code is an implementation of the program algorithm described in section 3.2 on page 3-4. Memory section: fl_prg Entry point: GPGMJ Parameters to be declared and initialized by the calling code are: PRG_bufaddr defines the destination start address. PRG_length defines the source buffer length. PRG_paddr defines the source buffer start address (data space).
Assembly Source for Algorithms PRELIMINARY * bits. For example, if the flash is programmed using a * * CLKOUT period of 50 ns, the flash can be reliably read * * back over the CLKOUT period range of 50 ns to 150 ns * * (6.67MHz–20 MHz). The programming pulse duration is * * 100 us, and a maximum of 150 pulses is applied per row.
PRELIMINARY Assembly Source for Algorithms * BASE_3 Used for buffer/row start addr * * BASE_4 Used for destination end addr * * BASE_5 Used for byte mask * ****************************************************** GPGMJ: SPLK #0,IMR ;MASK ALL INTERRUPTS SETC INTM ;GLOBALLY MASK ALL INTERRUPTS SPLK #0,ERROR ;Initialize error flag (no error). LACL PRG_paddr ;Get destination start address. SACL FL_ADRS ;Save as current address. ADD PRG_length ;Determine destination end addr.
PRELIMINARY Assembly Source for Algorithms BCND B ;fail, don’t continue. ;else, go to beginning ;of same row. ** If row done, then check if Array done. * ROW_DONE LACL FL_ADRS ;Check if end of array. SUB BASE_4 ;Subtract end addr. BCND DONE, GT ;If >0 then done. ** Else, go to next row. * LACL FL_ADRS B NEWROW ;Start new row. ** If here, then done. DONE CALL ARRAY ;Access flash in array mode. RET ;Return to calling program. ** If here, then unit failed to program.
PRELIMINARY Assembly Source for Algorithms SPLK #04000h,FL_ST ;FL_ST = FLASH1 CTRL REGS FL0 RET ************************************************************* .page ************************************************************* * THIS SECTION PROGRAMS THE VALUE STORED IN FL_DATA INTO * * THE FLASH ADDRESS DEFINED BY FL_ADRS. * * * * The following resources are used for temporary storage: * * AR6 Parameter passed to Delay * * SPAD1 Flash program and STOP commands * * SPAD2 Flash program + EXE command.
Assembly Source for Algorithms PRELIMINARY LACL FL_ST ;ACC => FLASH * SPLK #VER0,SPAD1 ;ACTIVATE VER0 * TBLW SPAD1 ;EXECUTE COMMAND * LAR AR6,#D10 ;SET DELAY * CALL DELAY,*,AR6 ;WAIT * CALL ARRAY ;ACCESS FLASH ARRAY * LACL FL_ADRS ;POINT TO ADRS * TBLR FL_DATA ;GET FLASH WORD 1x read * TBLR FL_DATA ; 2x read * TBLR FL_DATA ; 3x read * CALL REGS ;ACCESS FLASH REGISTERS * LACL FL_ST ;ACC => FLASH * SPLK #STOP,SPAD1 ;DEACTIVATE VER0 * TBLW SPAD1 ;EXECUTE COMMAND * LAR AR6,#D10 ;SET DELAY * CALL DELAY,*,AR6 ;
PRELIMINARY Assembly Source for Algorithms A.1.6 Subroutines Used By All Four Algorithms, SUTILS20.ASM This assembly file includes two subroutines that change the flash module access mode and one subroutine that performs software delays. More details on the individual functions are given in the comments. ************************************************************** ** Delay And Access Mode Subroutines ** * ** * TMS320F2XX Flash Utilities. ** * Revision: 2.0, 9/10/97 ** * Revision: 2.
PRELIMINARY Assembly Source for Algorithms SPLK #0000h,SPAD2 ***********The next instruction is for F240 only************* .if F24X = 1 ;Assemble for F24X only. OUT SPAD2,F24X_ACCS ;Enable F240 flash reg mode. ;SPAD1 is dummy value. .endif ************************************************************* .if F24X = 0 ;Assemble for F206 only. LACC FL_ST SUB #4000h BCND reg1,geq ;if address>= 4000h,set ;set reg mode for flash1 array OUT SPAD2,F_ACCESS0 ;Change mode of flash0.
PRELIMINARY C-Callable Interface to Flash Algorithms A.2 C-Callable Interface to Flash Algorithms The two functions erase() and program() are intended for in-application programming of the ’F20x/F24x flash module. These functions were written to be C callable, but they can also be called from assembly as long as the C stack calling convention is used.
C-Callable Interface to Flash Algorithms PRELIMINARY ;**Variables included from flash algorithms. .include ”svar20.h” ;Variable declarations .ref GCLR ;References clear algo. .ref GPGMJ ;References program algo. .ref GERS ;References erase algo. .ref FLWS ;References flash–write algo. ;**Parameters used by flash algorithms. .def PRG_bufaddr, PRG_paddr .def PRG_length, PARMS .def SEG_ST,SEG_END,PROTECT ************************************************************* VARS: .
PRELIMINARY C-Callable Interface to Flash Algorithms * passes, the flash is ready to be reprogrammed. The * * operations are performed on the segments of the flash * * module described by the parameter list: * * 1)PROTECT–defines which flash segments to protect.* * 2)SEG_ST –start address of segment to be erased. * * 3)SEG_END–end address of segment to be erased. * * To erase flash0 use erase(0xff00,0x0000,0x3fff). * * To erase flash1 use erase(0xff00,0x4000,0x7fff).
C-Callable Interface to Flash Algorithms PRELIMINARY ADD #1 ;Increment fail count. SACL ERS_COUNT ;Save new count. SUB #10 ;CHECK for max of 10. BCND ers_error,GT ;If ers_cout>10 then hard fail. CALL FLWS ;Else, try to recover from depletion. LACL ERROR ;Check for FLASH–WRITE error. BCND ers_error,neq ;If couldn’t recover, then hard fail. B ers_loop ;Else, try erase again. ers_error: LACL #0 ;Error while erasing. ers_done: LAR AR1,SV_AR1 ;Restore AR1. CLRC OVM ;Disable overflow.
PRELIMINARY C-Callable Interface to Flash Algorithms ;Begin C Preprocessing POPD *+ ; pop return address, push on s/w stack sar ar0,*+ ; save FP sar ar6,* ; save ar6 sbrk #3 ; Local variables (and parameters) are set up as follows: ; ;get arguments and place them properly – take them from ;the software stack and place them into their correct ;positions lar AR_PROTECT,*– lar AR_bufaddr,*– lar AR_paddr,*– lar AR_length,*– adrk #PRG_PARAMS+4 ; ar1 = next empty point on stack (SP) ; End C Preprocessing LDP #P
Sample Assembly Code to Erase and Reprogram the TMS320F206 PRELIMINARY A.3 Sample Assembly Code to Erase and Reprogram the TMS320F206 The algorithm files can be used from assembly in a straightforward manner. In general, the algorithms can reside anywhere in program space. However, the algorithms cannot be executed from the flash module that is being modified, and the algorithms must execute with zero wait states.
PRELIMINARY Sample Assembly Code to Erase and Reprogram the TMS320F206 ;data section used for * ;temporary variables, and * ;for passing parameters * ;to the flash algorithms. * ********************************************************* PROTECT .set PARMS ;Segment enable bits. * ********************************************************** ***Parameters needed for Programming algorithm. *** ********************************************************** PRG_bufaddr .
Sample Assembly Code to Erase and Reprogram the TMS320F206 PRELIMINARY SUB #10 BCND ers_error,GT CALL LACL BCND B ;CHECK for max of 10. ;If ers_cout>10 then hard ;fail. FLWS ;Else, try to recover from ;depletion. ERROR ;Check for FLASH–WRITE error. ers_error,neq ;If couldn’t recover, then ;hard fail. ers_loop ;Else, try erase again. ers_error: ******************************************************** ** If here, then an unrecoverable error has occurred ** ** during erase.
PRELIMINARY Sample Assembly Code to Erase and Reprogram the TMS320F206 prg_error: ******************************************************** ** If here, then an error has occurred during ** ** programming. In an actual application, the system ** ** takes some action to indicate that service is ** ** required. ** ******************************************************** B prg_error ;Error while programming.
Sample Assembly Code to Erase and Reprogram the TMS320F206 PAGE 1: PRELIMINARY /* DM – Data memory */ BLK_B2: origin = 0x60,length = 0x20 DSARAM: origin = 0xc00, length = 0xC00 EX1_DM: origin = 0x4000, length = 0x4000 B1: origin = 0x300, length = 0x1ff /*BLOCK B2 /*Use 3K of SARAM for data DON=1 /*External data RAM /*B1 Ram (Used for algo vars ) */ */ */ */ } /*************************Section Allocation************************************/ SECTIONS { .text : {} > PSARAM PAGE 0 /* asmexamp.
PRELIMINARY Sample C Code to Erase and Reprogram the TMS320F206 A.4 Sample C Code to Erase and Reprogram the TMS320F206 Because the algorithm implementations do not follow the C-calling convention of the ’C2000 C environment, they cannot be used directly from C. The assembly code of section A.2, C-Callable Interface to Flash Algorithms, is provided as a C-callable interface to the programming algorithms. The following C source file and linker command file provide a working example for the ’F206.
Sample C Code to Erase and Reprogram the TMS320F206 PRELIMINARY { /*Flash fails programming, EXIT*/ while(1){} /*Spin here forever*/ } } else { /*Flash fails erase, EXIT*/ while(1){} /*Spin here forever*/ } } A.4.2 Linker Command File for TMS320F206 Sample C Code /*************************************************************************/ /* Filename: F206_SA.CMD */ /* Description: Linker command file for ’F206 example of on–chip flash */ /* programming from C code.
PRELIMINARY FLASH0: FLASH1: PSARAM: B0: Sample C Code to Erase and Reprogram the TMS320F206 origin origin origin origin = = = = 0x0000, 0x4000, 0x8000, 0xff00, PAGE 1: /* DM – Data memory length length length length = = = = 0x3fff 0x3fff 0x400 /*Use 1K of SARAM for PROGRAM*/ 0x1ff */ BLK_B2: DSARAM: origin = origin = 0x60, 0xc00, length = length = EX1_DM: B1: origin = origin = 0x4000, 0x300, length = length = 0x20 /*BLOCK B2 */ 0xC00 /*Use 3K of SARAM for data */ /*DON=1*/ 0x4000 /*Externa
Sample Assembly Code to Erase and Reprogram the TMS320F240 PRELIMINARY A.5 Sample Assembly Code to Erase and Reprogram the TMS320F240 The algorithm files can be used from assembly in a straightforward manner. In general, the algorithms can reside anywhere in program space. However, the algorithms cannot be executed from the flash module that is being modified, and the algorithms must execute with zero wait states.
PRELIMINARY Sample Assembly Code to Erase and Reprogram the TMS320F240 ;**Variables included from flash algorithms. .include ”svar20.h” ;Variable declarations .ref GCLR ;References clear algo. .ref GPGMJ ;References program algo. .ref GERS ;References erase algo. .ref FLWS ;References flash–write algo. ;**Parameters used by flash algorithms. .def PRG_bufaddr, PRG_paddr .def PRG_length, PARMS .def SEG_ST,SEG_END,PROTECT ;**F240 Register definitions RTICR .set 07027h ;RTI Control Register WDCR .
Sample Assembly Code to Erase and Reprogram the TMS320F240 PRELIMINARY F240INIT: ;Set Data Page pointer to page 1 of the ;peripheral frame LDP #DP_PF1 ;Page DP_PF1 includes WET through * ;EINT frames ;initialize WDT registers SPLK #06Fh, WDCR ;clear WDFLAG, Disable WDT ;(if Vpp=5V), set WDT ;for 1 second overflow (max) SPLK #07h, RTICR ;clear RTI Flag, ;set RTI for 1 second overflow ;(max) ;EVM 10–MHz oscillator settings.
PRELIMINARY Sample Assembly Code to Erase and Reprogram the TMS320F240 depletion: LACL ADD SACL SUB BCND CALL ERS_COUNT #1 ERS_COUNT #10 ers_error,GT FLWS LACL BCND ERROR ers_error,neq B ers_loop ;Get erase fail count. ;Increment fail count. ;Save new count. ;CHECK for max of 10. ;If ers_cout>10 then hard fail. ;Else, try to recover from ;depletion. ;Check for FLASH–WRITE error. ;If couldn’t recover, then hard ;fail. ;Else, Try erase again.
Sample Assembly Code to Erase and Reprogram the TMS320F240 PRELIMINARY ************************************************************** ** Now that the data to be programmed is ready, the ** ** programming algorithm is invoked. Note: Four parameters ** ** must be initialized before calling the algorithm. ** ************************************************************** LDP #PARMS **********Put parameters where they belong.
PRELIMINARY Sample Assembly Code to Erase and Reprogram the TMS320F240 A.5.2 Linker Command File for TMS320F240 Sample Assembly Code /************************************************************/ /* Filename: ASMEXA24.CMD */ /* Description: Linker command file for ’F240 example of */ /* on–chip flash programming from assembly. This command */ /* file links the example to addr 0x8000 of the off–chip */ /* pgm RAM, so that the debugger can be used to set */ /* breakpoints. */ /* Notes: */ /* 1.
Sample Assembly Code to Erase and Reprogram the TMS320F240 PRELIMINARY /*All these fl_prg : fl_clr : fl_ers : fl_wrt : DLY : REG : ARY : PRG_data : sections are for flash programming.
PRELIMINARY Using the Algorithms With C Code to Erase and Reprogram the ’F240 A.6 Using the Algorithms With C Code to Erase and Reprogram the ’F240 Because the algorithm implementations do not follow the C-calling convention of the ’C2000 C environment, they cannot be used directly from C. The assembly code of section A.2, C-Callable Interface to Flash Algorithms, is provided as a C-callable interface to the programming algorithms.
Using the Algorithms With C Code to Erase and Reprogram the ’F240 PRELIMINARY extern int erase(); /* Declare external func for flash erase.
PRELIMINARY Using the Algorithms With C Code to Erase and Reprogram the ’F240 /************************Command Line Options**************************/ –cr /*Use Ram init model. */ –heap 0x0 /*No heap needed for this example. */ –stack 0x96 /*150 word stack is enough for this example. */ –x /*Force re–reading of libraries. */ –l c:\dsptools\fix\rts2xx.lib –o sample24.out –m sample24.map /*****************************Input Files******************************/ sample24.
PRELIMINARY Using the Algorithms With C Code to Erase and Reprogram the ’F240 .bss .cinit .const :{} > B1 PAGE 1 :{} > B1 PAGE 1 : load = EXTRAM PAGE 0, run = DSRAM PAGE 1 { /* GET RUN ADDRESS */ __const_run = .; /* MARK LOAD ADDRESS */ *(.c_mark) /* ALLOCATE .const */ *(.const) /* COMPUTE LENGTH */ __const_length = .– __const_run; } .data :{} > B1 PAGE 1 .stack :{} > B1 PAGE 1 /*C stack. */ } A.6.
PRELIMINARY Using the Algorithms With C Code to Erase and Reprogram the ’F240 OR #06fh ; set WDDIS bit and WDCHK2:0 bits, WDCLK to max. SACL WDCR ; write ACC out to WDTCR ***************************************************************************** * Step 9. Deallocate the local frame * ***************************************************************************** SBRK 1+1 ; deallocate frame, point to saved FP *************************************************************************** * Step 10.
Using the Algorithms With C Code to Erase and Reprogram the ’F240 PRELIMINARY * Step 5.
PRELIMINARY Index Index A access modes code for changing A-25 array access 2-5, 2-10, 2-11, 2-16, 3-8 register access 2-5, 2-10, 2-11, 3-11 access–control register 2-5 to 2-7 modifying in TMS320F206 2-6 modifying in TMS320F24x 2-7 reading in TMS320F206 2-6 accessing the flash module 2-5 address complementing 3-11 algorithms erase 3-10 to 3-13 flash–write 3-14 to 3-18 in the overall flow 3-2 limiting number of bits to be programmed 2-13 programming 3-4 to 3-9 applying a single erase pulse 3-11 applying a s
PRELIMINARY Index erase algorithm assembly code (SERA2x.ASM) described 3-10 to 3-13 flow diagram 3-13 in overall flow 3-10 erase() function (C code listing) A-27 erase operation described 2-14 following flash–write operation 2-15 frequency range 3-12 logic levels 2-4 role of WDATA 2-11 VER1 read mode 2-12 verification of erased bits 2-12 worst–case voltage for reading erased cell erase protection erase pulse 3-11 example for TMS320F206 assembly code A-32, A-40 C code that calls flash.
PRELIMINARY Index M margin determining 3-5, 3-11 ensuring data retention 1-2 improving 3-12 in programming 2-13 restoring after flash–write operation 2-15 special read modes for ensuring 2-12 masking data in program operation 3-8 memory maps 1-4 MODE bit 2-6 See also flash access–control register mode selection for access 2-6 modifying the array contents 2-2, 2-16 module–control register 2-8 multiple reads at same location 3-5, 3-17 N notational conventions R read mode, standard 2-12 read modes 2-12 rea
PRELIMINARY Index subroutines used by all algorithms (SUTILS2x.ASM) A-25 SUTILS2x.ASM file (code for subroutines) A-25 SVAR2x.H file (header file for constants and variables) A-2 W T test register (TST) 2-6, 2-8, 2-10 U uniformity of charge 3-5, 3-9 unintentional erasure, protection 2-16 using the algorithms with assembly code A-32, A-40 using the algorithms with C code A-37, A-47 V variable CPU clock rate 3-5, 3-12, 3-17 variable declaration file. See header file for constants and variables (SVAR2x.
